Valid Strobes; Basic Timing - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.5.2

Valid Strobes

Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the 5' signal is valid for both the upper and the lower half of the data bus. In a write,
the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.
Table 6.3 Data Buses Used and Valid Strobes
Access
Area Size
8-bit access Byte
space
16-bit access Byte
space
Word
Note: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
6.5.3

Basic Timing

8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
/:5 pin is always fixed high. Wait states can be inserted.
Read/
Write Address
Read —
Write —
Read Even
Odd
Write Even
Odd
Read —
Write —
Valid Upper Data Bus
Strobe (D15 to D8)
5'
Valid
+:5
5'
Valid
Invalid
+:5
Valid
/:5
Hi-Z
5'
Valid
+:5, /:5
Valid
Rev. 1.0, 09/01, page 143 of 904
Lower Data Bus
(D7 to D0)
Invalid
Hi-Z
Invalid
Valid
Hi-Z
Valid
Valid
Valid