Hitachi HD64F2377 Manuals

Manuals and User Guides for Hitachi HD64F2377. We have 1 Hitachi HD64F2377 manual available for free PDF download: Hardware Manual

Hitachi HD64F2377 Hardware Manual (949 pages)

16 Bit Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 4.57 MB

- 7
  Table of Contents
- 25
  Overview
- 36
  Electrical Characteristics
45
Section 1 Overview
- 45
  Features
- 46
  Block Diagram
- 47
  Pin Description
  - 47
    Pin Arrangement
  - 48
    Pin Arrangement in Each Operating Mode
  - 54
    Pin Functions
61
Section 2 CPU
- 61
  Features
- 64
  CPU Operating Modes
  - 64
    Normal Mode
  - 65
    Advanced Mode
- 68
  Address Space
- 69
  Register Configuration
  - 70
    General Registers
  - 71
    Program Counter (PC)
  - 71
    Extended Register (EXR)
  - 72
    Condition-Code Register (CCR)
  - 74
    Initial Register Values
- 74
  Data Formats
  - 74
    General Register Data Formats
  - 76
    Memory Data Formats
- 77
  Instruction Set
  - 78
    Table of Instructions Classified By Function
  - 87
    Basic Instruction Formats
- 88
  Addressing Modes and Effective Address Calculation
- 94
  Processing States
- 95
  Usage Notes
  - 95
    Note On Bit Manipulation Instructions
97
Section 3 MCU Operating Modes
- 97
  Operating Mode Selection
- 98
  Register Descriptions
  - 98
    Mode Control Register (MDCR)
  - 98
    System Control Register (SYSCR)
- 100
  Operating Mode Descriptions
  - 100
    Mode 1
  - 100
    Mode 2
  - 100
    Mode 3
  - 100
    Mode 4
  - 100
    Mode 5
  - 101
    Mode 6
  - 101
    Mode 7
  - 102
    Pin Functions
- 103
  Memory Map in Each Operating Mode
107
Section 4 Exception Handling
- 107
  Exception Handling Types and Priority
- 107
  Exception Sources and Exception Vector Table
- 109
  Reset
- 112
  Traces
- 112
  Interrupts
- 113
  Trap Instruction
- 114
  Stack Status After Exception Handling
- 115
  Usage Notes
117
Section 5 Interrupt Controller
- 117
  Features
- 119
  Input/Output Pins
- 119
  Register Descriptions
- 132
  Interrupt Sources
  - 132
    External Interrupts
  - 133
    Internal Interrupts
- 134
  Interrupt Exception Handling Vector Table
- 139
  Interrupt Control Modes and Interrupt Operation
  - 139
    Interrupt Control Mode 0
  - 141
    Interrupt Control Mode 2
  - 142
    Interrupt Exception Handling Sequence
  - 144
    Interrupt Response Times
  - 145
    DTC and DMAC Activation By Interrupt
- 146
  Usage Notes
149
Section 6 Bus Controller (BSC)
- 149
  Features
- 151
  Input/Output Pins
- 153
  Register Descriptions
- 179
  Bus Control
  - 179
    Area Division
  - 181
    Bus Specifications
  - 182
    Memory Interfaces
  - 184
    Chip Select Signals
- 185
  Basic Bus Interface
  - 185
    Data Size and Data Alignment
  - 187
    Valid Strobes
  - 187
    Basic Timing
  - 195
    Wait Control
  - 197
    Read Strobe ( RD ) Timing
  - 198
    Extension of Chip Select ( CS ) Assertion Period
- 199
  DRAM Interface
  - 199
    Setting DRAM Space
  - 200
    Address Multiplexing
  - 201
    Data Bus
  - 202
    Pins Used for DRAM Interface
  - 203
    Basic Timing
  - 204
    Column Address Output Cycle Control
  - 205
    Row Address Output State Control
  - 207
    Precharge State Control
  - 208
    Wait Control
  - 211
    Byte Access Control
  - 212
    Burst Operation
  - 216
    Refresh Control
  - 221
    DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
- 224
  Synchronous DRAM Interface
  - 224
    Setting Continuous Synchronous DRAM Space
  - 225
    Address Multiplexing
  - 226
    Data Bus
  - 226
    Pins Used for Synchronous DRAM Interface
  - 228
    Synchronous DRAM Clock
  - 228
    Basic Timing
  - 230
    CAS Latency Control
  - 232
    Row Address Output State Control
  - 234
    Precharge State Count
  - 236
    Bus Cycle Control in Write Cycle
  - 237
    Byte Access Control
  - 239
    Burst Operation
  - 243
    Refresh Control
  - 248
    Mode Register Setting of Synchronous DRAM
  - 250
    DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface
- 255
  Burst ROM Interface
  - 255
    Basic Timing
  - 257
    Wait Control
  - 257
    Write Access
- 258
  Idle Cycle
  - 258
    Operation
  - 274
    Pin States in Idle Cycle
- 274
  Write Data Buffer Function
- 275
  Bus Release
  - 275
    Operation
  - 277
    Pin States in External Bus Released State
  - 278
    Transition Timing
- 280
  Bus Arbitration
  - 280
    Operation
  - 280
    Bus Transfer Timing
- 282
  Bus Controller Operation in Reset
- 282
  Usage Notes
285
Section 7 DMA Controller (DMAC)
- 285
  Features
- 287
  Input/Output Pins
- 287
  Register Descriptions
- 313
  Activation Sources
- 315
  Operation
  - 315
    Transfer Modes
  - 317
    Sequential Mode
  - 319
    Idle Mode
  - 321
    Repeat Mode
  - 324
    Single Address Mode
  - 327
    Normal Mode
  - 330
    Block Transfer Mode
  - 336
    Basic Bus Cycles
  - 336
    DMA Transfer (Dual Address Mode) Bus Cycles
  - 344
    DMA Transfer (Single Address Mode) Bus Cycles
  - 350
    Write Data Buffer Function
  - 351
    Multi-Channel Operation
  - 352
    Relation Between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC
  - 353
    DMAC and NMI Interrupts
  - 353
    Forced Termination of DMAC Operation
  - 354
    Clearing Full Address Mode
- 355
  Interrupt Sources
- 356
  Usage Notes
  - 356
    DMAC Register Access During Operation
  - 358
    Module Stop
  - 358
    Write Data Buffer Function
  - 358
    TEND Output
  - 359
    Activation By Falling Edge On DREQ Pin
  - 360
    Activation Source Acceptance
  - 360
    Internal Interrupt After End of Transfer
  - 360
    Channel Re-Setting
361
Section 8 EXDMA Controller
- 361
  Features
- 363
  Input/Output Pins
- 363
  Register Descriptions
- 375
  Operation
  - 375
    Transfer Modes
  - 376
    Address Modes
  - 380
    DMA Transfer Requests
  - 380
    Bus Modes
  - 382
    Transfer Modes
  - 384
    Repeat Area Function
  - 386
    Registers During DMA Transfer Operation
  - 390
    Channel Priority Order
  - 393
    EXDMAC Bus Cycles (Dual Address Mode)
  - 398
    EXDMAC Bus Cycles (Single Address Mode)
  - 403
    Examples of Operation Timing in Each Mode
  - 416
    Ending DMA Transfer
  - 417
    Relationship Between EXDMAC and Other Bus Masters
- 417
  Interrupt Sources
- 420
  Usage Notes
423
Section 9 Data Transfer Controller (DTC)
- 423
  Features
- 424
  Register Configuration
- 428
  Activation Sources
- 429
  Location of Register Information and DTC Vector Table
- 432
  Operation
  - 434
    Normal Mode
  - 435
    Repeat Mode
  - 436
    Block Transfer Mode
  - 437
    Chain Transfer
  - 438
    Interrupts
  - 439
    Operation Timing
  - 440
    Number of DTC Execution States
- 441
  Procedures for Using DTC
  - 441
    Activation By Interrupt
  - 441
    Activation By Software
- 441
  Examples of Use of the DTC
  - 441
    Normal Mode
  - 442
    Chain Transfer
  - 443
    Chain Transfer When Counter = 0
  - 444
    Software Activation
- 445
  Usage Notes
  - 445
    Module Stop Mode Setting
  - 445
    On-Chip RAM
  - 445
    DTCE Bit Setting
  - 445
    DMAC Transfer End Interrupt
  - 445
    Chain Transfer
447
Section 10 I/O Ports
- 452
  Port 1
  - 452
    Port 1 Data Direction Register (P1DDR)
  - 452
    Port 1 Data Register (P1DR)
  - 453
    Port 1 Register (PORT1)
  - 453
    Pin Functions
- 463
  Port 2
  - 463
    Port 2 Data Direction Register (P2DDR)
  - 463
    Port 2 Data Register (P2DR)
  - 464
    Port 2 Register (PORT2)
  - 465
    Pin Functions
- 473
  Port 3
  - 473
    Port 3 Data Direction Register (P3DDR)
  - 474
    Port 3 Data Register (P3DR)
  - 474
    Port 3 Register (PORT3)
  - 475
    Port 3 Open Drain Control Register (P3ODR)
  - 476
    Port Function Control Register 2 (PFCR2)
  - 477
    Pin Functions
- 480
  Port 4
  - 480
    Port 4 Register (PORT4)
  - 480
    Pin Functions
- 482
  Port 5
  - 482
    Port 5 Data Direction Register (P5DDR)
  - 482
    Port 5 Data Register (P5DR)
  - 483
    Port 5 Register (PORT5)
  - 483
    Pin Functions
- 485
  Port 6
  - 485
    Port 6 Data Direction Register (P6DDR)
  - 485
    Port 6 Data Register (P6DR)
  - 486
    Port 6 Register (PORT6)
  - 486
    Pin Functions
- 489
  Port 8
  - 489
    Port 8 Data Direction Register (P8DDR)
  - 490
    Port 8 Data Register (P8DR)
  - 490
    Port 8 Register (PORT8)
  - 491
    Pin Functions
- 495
  Port 9
  - 495
    Port 9 Register (PORT9)
  - 495
    Pin Functions
- 497
  Port a
  - 498
    Port a Data Direction Register (PADDR)
  - 499
    Port a Data Register (PADR)
  - 499
    Port a Register (PORTA)
  - 500
    Port a MOS Pull-Up Control Register (PAPCR)
  - 500
    Port a Open Drain Control Register (PAODR)
  - 500
    Port Function Control Register 1 (PFCR1)
  - 502
    Pin Functions
  - 503
    Port a MOS Input Pull-Up States
- 504
  Port B
  - 504
    Port B Data Direction Register (PBDDR)
  - 505
    Port B Data Register (PBDR)
  - 505
    Port B Register (PORTB)
  - 506
    Port B MOS Pull-Up Control Register (PBPCR)
  - 506
    10.10.5 Pin Functions
  - 507
    10.10.6 Port B MOS Input Pull-Up States
- 508
  Port C
  - 508
    Port C Data Direction Register (PCDDR)
  - 509
    Port C Data Register (PCDR)
  - 509
    Port C Register (PORTC)
  - 510
    Port C MOS Pull-Up Control Register (PCPCR)
  - 510
    10.11.5 Pin Functions
  - 511
    10.11.6 Port C MOS Input Pull-Up States
- 512
  Port D
  - 512
    Port D Data Direction Register (PDDDR)
  - 512
    Port D Data Register (PDDR)
  - 513
    Port D Register (PORTD)
  - 513
    Port D Pull-Up Control Register (PDPCR)
  - 513
    10.12.5 Pin Functions
  - 514
    10.12.6 Port D MOS Input Pull-Up States
- 515
  Port E
  - 515
    Port E Data Direction Register (PEDDR)
  - 516
    Port E Data Register (PEDR)
  - 516
    Port E Register (PORTE)
  - 517
    Port E Pull-Up Control Register (PEPCR)
  - 517
    10.13.5 Pin Functions
  - 518
    10.13.6 Port E MOS Input Pull-Up States
- 519
  Port F
  - 519
    Port F Data Direction Register (PFDDR)
  - 521
    Port F Data Register (PFDR)
  - 521
    Port F Register (PORTF)
  - 522
    10.14.4 Pin Functions
- 526
  Port G
  - 526
    Port G Data Direction Register
  - 528
    Port G Data Register
  - 528
    Port G Register (PORTG)
  - 529
    Port Function Control Register 0 (PFCR0)
  - 529
    Pin Functions
- 532
  Port H
  - 532
    Port H Data Direction Register (PHDDR)
  - 534
    Port H Data Register (PHDR)
  - 534
    Port H Register (PORTH)
  - 535
    10.16.4 Pin Functions
537
Section 11 16-Bit Timer Pulse Unit (TPU)
- 537
  Features
- 541
  Input/Output Pins
- 542
  Register Descriptions
  - 543
    Timer Control Register (TCR)
  - 549
    Timer Mode Register (TMDR)
  - 550
    Timer I/O Control Register (TIOR)
  - 568
    Timer Interrupt Enable Register (TIER)
  - 570
    Timer Status Register (TSR)
  - 572
    Timer Counter (TCNT)
  - 573
    Timer General Register (TGR)
  - 573
    Timer Start Register (TSTR)
  - 574
    Timer Synchronous Register (TSYR)
- 575
  Operation
  - 575
    Basic Functions
  - 580
    Synchronous Operation
  - 582
    Buffer Operation
  - 585
    Cascaded Operation
  - 587
    PWM Modes
  - 592
    Phase Counting Mode
- 598
  Interrupts
- 600
  DTC Activation
- 600
  DMAC Activation
- 600
  A/D Converter Activation
- 601
  Operation Timing
  - 601
    Input/Output Timing
  - 604
    Interrupt Signal Timing
- 607
  Usage Notes
615
Section 12 Programmable Pulse Generator (PPG)
- 615
  Features
- 617
  Input/Output Pins
- 617
  Register Descriptions
- 625
  Operation
- 633
  Usage Notes
  - 633
    Module Stop Mode Setting
  - 633
    Operation of Pulse Output Pins
635
Section 13 8-Bit Timers (TMR)
- 635
  Features
- 637
  Input/Output Pins
- 637
  Register Descriptions
  - 637
    Timer Counter (TCNT)
  - 638
    Time Constant Register a (TCORA)
  - 638
    Time Constant Register B (TCORB)
  - 638
    Timer Control Register (TCR)
  - 640
    Timer Control/Status Register (TCSR)
- 643
  Operation
  - 643
    Pulse Output
- 644
  Operation Timing
- 647
  Operation with Cascaded Connection
  - 647
    16-Bit Counter Mode
  - 648
    Compare Match Count Mode
- 648
  Interrupts
  - 648
    Interrupt Sources and DTC Activation
  - 649
    A/D Converter Activation
- 650
  Usage Notes
657
Section 14 Watchdog Timer
- 657
  Features
- 658
  Input/Output Pin
- 658
  Register Descriptions
- 662
  Operation
  - 662
    Watchdog Timer Mode
  - 663
    Interval Timer Mode
- 664
  Interrupts
- 664
  Usage Notes
669
Section 15 Serial Communication Interface (SCI, Irda)
- 669
  Features
- 672
  Input/Output Pins
- 672
  Register Descriptions
  - 674
    Receive Shift Register (RSR)
  - 674
    Receive Data Register (RDR)
  - 674
    Transmit Data Register (TDR)
  - 674
    Transmit Shift Register (TSR)
  - 674
    Serial Mode Register (SMR)
  - 677
    Serial Control Register (SCR)
  - 682
    Serial Status Register (SSR)
  - 689
    Smart Card Mode Register (SCMR)
  - 690
    Bit Rate Register (BRR)
  - 699
    Irda Control Register (Ircr)
  - 700
    Serial Extension Mode Register (SEMR)
- 702
  Operation in Asynchronous Mode
- 713
  Multiprocessor Communication Function
  - 715
    Multiprocessor Serial Data Transmission
  - 717
    Multiprocessor Serial Data Reception
- 720
  Operation in Clocked Synchronous Mode
- 729
  Operation in Smart Card Interface Mode
- 739
  Irda Operation
- 742
  SCI Interrupts
  - 742
    Interrupts in Normal Serial Communication Interface Mode
  - 743
    Interrupts in Smart Card Interface Mode
- 745
  Usage Notes
751
Section 16 I C Bus Interface2 (IIC2) (Option)
- 751
  Features
- 753
  Input/Output Pins
- 753
  Register Description
  - 754
    C Bus Control Register a (ICCRA)
  - 756
    C Bus Control Register B (ICCRB)
  - 757
    C Bus Mode Register (ICMR)
  - 759
    C Bus Interrupt Enable Register (ICIER)
  - 761
    C Bus Status Register (ICSR)
  - 763
    Slave Address Register (SAR)
  - 763
    C Bus Transmit Data Register (ICDRT)
  - 763
    C Bus Receive Data Register (ICDRR)
  - 763
    C Bus Shift Register (ICDRS)
- 764
  Operation
  - 764
    C Bus Format
  - 765
    Master Transmit Operation
  - 767
    Master Receive Operation
  - 769
    Slave Transmit Operation
  - 771
    Slave Receive Operation
  - 773
    Noise Canceler
  - 773
    Example of Use
- 778
  Interrupt Request
- 779
  Bit Synchronous Circuit
781
Section 17 A/D Converter
- 781
  Features
- 782
  Input/Output Pins
- 783
  Register Description
- 788
  Operation
  - 788
    Single Mode
  - 788
    Scan Mode
  - 789
    Input Sampling and A/D Conversion Time
  - 790
    External Trigger Input Timing
- 791
  Interrupts
- 791
  A/D Conversion Precision Definitions
- 793
  Usage Notes
797
Section 18 D/A Converter
- 797
  Features
- 798
  Input/Output Pins
- 798
  Register Description
  - 798
    D/A Data Registers 0 to
  - 799
    D/A Control Registers 01, 23, and 45 (DACR01, DACR23, DACR45)
- 804
  Operation
- 805
  Usage Notes
  - 805
    Setting for Module Stop Mode
  - 805
    D/A Output Hold Function in Software Standby Mode
807
Section 19 RAM
809
Section 20 Flash Memory (F-ZTAT Version)
- 809
  Features
- 810
  Mode Transitions
- 814
  Block Configuration
- 816
  Input/Output Pins
- 816
  Register Descriptions
- 822
  On-Board Programming Modes
  - 822
    Boot Mode
  - 825
    User Program Mode
- 826
  Flash Memory Emulation in RAM
- 828
  Flash Memory Programming/Erasing
- 832
  Program/Erase Protection
  - 832
    Hardware Protection
  - 832
    Software Protection
  - 832
    Error Protection
- 833
  Programmer Mode
- 833
  Power-Down States for Flash Memory
- 833
  Usage Notes
837
Section 21 Clock Pulse Generator
- 837
  Register Description
  - 837
    System Clock Control Register (SCKCR)
  - 839
    PLL Control Register (PLLCR)
- 839
  Oscillator
  - 840
    Connecting a Crystal Oscillator
  - 841
    External Clock Input
- 842
  PLL Circuit
- 843
  Frequency Divider
- 843
  Usage Notes
  - 843
    Notes On Clock Pulse Generator
  - 843
    Notes On Oscillator
  - 844
    Notes On Board Design
845
Section 22 Power-Down Modes
- 848
  Register Descriptions
- 852
  Operation
  - 852
    Clock Division Mode
  - 852
    Sleep Mode
  - 853
    Software Standby Mode
  - 855
    Hardware Standby Mode
  - 856
    Module Stop Mode
  - 857
    All-Module-Clocks-Stop Mode
- 857
  Ø Clock Output Control
- 858
  Usage Notes
859
Section 23 List of Registers
- 859
  Register Addresses (Address Order)
- 871
  Register Bits
- 885
  Register States in Each Operating Mode
895
Section 24 Electrical Characteristics
- 895
  Absolute Maximum Ratings
- 896
  DC Characteristics
- 899
  AC Characteristics
  - 900
    Clock Timing
  - 902
    Control Signal Timing
  - 904
    Bus Timing
  - 925
    DMAC and EXDMAC Timing
  - 929
    Timing of On-Chip Peripheral Modules
- 934
  A/D Conversion Characteristics
- 934
  D/A Conversion Characteristics
- 935
  Flash Memory Characteristics
- 937
  Usage Note
939
Appendix
- 939
  I/O Port States in Each Pin State
- 947
  Product Lineup
- 948
  Package Dimensions

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Hitachi HD64F2377 Manuals

Manuals and User Guides for Hitachi HD64F2377. We have 1 Hitachi HD64F2377 manual available for free PDF download: Hardware Manual

Hitachi HD64F2377 Hardware Manual (949 pages)

Table of Contents

45 Section 1 Overview

61 Section 2 CPU

97 Section 3 MCU Operating Modes

107 Section 4 Exception Handling

117 Section 5 Interrupt Controller

149 Section 6 Bus Controller (BSC)

285 Section 7 DMA Controller (DMAC)

361 Section 8 EXDMA Controller

423 Section 9 Data Transfer Controller (DTC)

447 Section 10 I/O Ports

537 Section 11 16-Bit Timer Pulse Unit (TPU)

615 Section 12 Programmable Pulse Generator (PPG)

635 Section 13 8-Bit Timers (TMR)

657 Section 14 Watchdog Timer

669 Section 15 Serial Communication Interface (SCI, Irda)

751 Section 16 I C Bus Interface2 (IIC2) (Option)

781 Section 17 A/D Converter

797 Section 18 D/A Converter

807 Section 19 RAM

809 Section 20 Flash Memory (F-ZTAT Version)

837 Section 21 Clock Pulse Generator

845 Section 22 Power-Down Modes

859 Section 23 List of Registers

895 Section 24 Electrical Characteristics

939 Appendix

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45
Section 1 Overview

61
Section 2 CPU

97
Section 3 MCU Operating Modes

107
Section 4 Exception Handling

117
Section 5 Interrupt Controller

149
Section 6 Bus Controller (BSC)

285
Section 7 DMA Controller (DMAC)

361
Section 8 EXDMA Controller

423
Section 9 Data Transfer Controller (DTC)

447
Section 10 I/O Ports

537
Section 11 16-Bit Timer Pulse Unit (TPU)

615
Section 12 Programmable Pulse Generator (PPG)

635
Section 13 8-Bit Timers (TMR)

657
Section 14 Watchdog Timer

669
Section 15 Serial Communication Interface (SCI, Irda)

751
Section 16 I C Bus Interface2 (IIC2) (Option)

781
Section 17 A/D Converter

797
Section 18 D/A Converter

807
Section 19 RAM

809
Section 20 Flash Memory (F-ZTAT Version)

837
Section 21 Clock Pulse Generator

845
Section 22 Power-Down Modes

859
Section 23 List of Registers

895
Section 24 Electrical Characteristics

939
Appendix