11.10.8 Contention Between Tgr Read And Input Capture - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 11.48 Contention between Buffer Register Write and Compare Match

11.10.8 Contention between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 11.49 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 11.49 Contention between TGR Read and Input Capture
TGR write cycle
T1 T2
Buffer register
address
N M
N
TGR read cycle
T1 T2
TGR address
X M
M
Buffer register write data
Rev. 1.0, 09/01, page 567 of 904