Interrupts - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Register information
DTC vector
address
9.5.5

Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
Rev. 1.0, 09/01, page 394 of 904
start address
Figure 9.8 Operation of Chain Transfer
Register information
CHNE=1
Register information
CHNE=0
Source
Destination
Source
Destination