Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 16

10.16 Port H ................................................................................................................................488
10.16.1 Port H Data Direction Register (PHDDR) ...........................................................488
10.16.2 Port H Data Register (PHDR) ..............................................................................490
10.16.3 Port H Register (PORTH) ....................................................................................490
10.16.4 Pin Functions .......................................................................................................491
Section 11 16-Bit Timer Pulse Unit (TPU) .......................................................493
11.1 Features .............................................................................................................................493
11.2 Input/Output Pins ..............................................................................................................497
11.3 Register Descriptions ........................................................................................................498
11.3.1 Timer Control Register (TCR) .............................................................................499
11.3.2 Timer Mode Register (TMDR) ............................................................................505
11.3.3 Timer I/O Control Register (TIOR) .....................................................................506
11.3.4 Timer Interrupt Enable Register (TIER) ..............................................................524
11.3.5 Timer Status Register (TSR) ................................................................................526
11.3.6 Timer Counter (TCNT)........................................................................................528
11.3.7 Timer General Register (TGR) ............................................................................529
11.3.8 Timer Start Register (TSTR)................................................................................529
11.3.9 Timer Synchronous Register (TSYR) ..................................................................530
11.4 Operation...........................................................................................................................531
11.4.1 Basic Functions ....................................................................................................531
11.4.2 Synchronous Operation........................................................................................536
11.4.3 Buffer Operation ..................................................................................................538
11.4.4 Cascaded Operation .............................................................................................541
11.4.5 PWM Modes ........................................................................................................543
11.4.6 Phase Counting Mode ..........................................................................................548
11.5 Interrupts ...........................................................................................................................554
11.6 DTC Activation.................................................................................................................556
11.7 DMAC Activation.............................................................................................................556
11.8 A/D Converter Activation .................................................................................................556
11.9 Operation Timing..............................................................................................................557
11.9.1 Input/Output Timing ............................................................................................557
11.9.2 Interrupt Signal Timing........................................................................................560
11.10 Usage Notes ......................................................................................................................563
11.10.1 Module Stop Mode Setting ..................................................................................563
11.10.2 Input Clock Restrictions.......................................................................................563
11.10.3 Caution on Cycle Setting .....................................................................................564
11.10.4 Contention between TCNT Write and Clear Operations .....................................564
11.10.5 Contention between TCNT Write and Increment Operations ..............................565
11.10.6 Contention between TGR Write and Compare Match .........................................566
11.10.7 Contention between Buffer Register Write and Compare Match ........................566
11.10.8 Contention between TGR Read and Input Capture..............................................567
11.10.9 Contention between TGR Write and Input Capture.............................................568
Rev. 1.0, 09/01, page xvi of xliv