Byte Access Control - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.11

Byte Access Control

When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are
used for the control signals needed for byte access.
Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of
connection of byte control by DQMU and DQML.
ø
SDRAMø
Address bus
Precharge-sel
CKE
DQMU
DQML
Upper data bus
Lower data bus
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)
T T
p r
Column address Row address
Row address
PALL ACTV
Figure 6.49 DQMU and DQML Control Timing
T T
c1 cl
Column address
High
High
High-Z
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Rev. 1.0, 09/01, page 193 of 904
T
c2
NOP