Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 210

ø
Address bus
(
,
( )
Read
( )
Data bus
,
( )
Write
( )
Data bus
Note: Downward arrows indicate the timing of
n = 2 to 5
Rev. 1.0, 09/01, page 166 of 904
T T
p r
Row address
)
Figure 6.27 Example of Wait State Insertion Timing
(3-State Column Address Output)
By program wait
T T
c1 w
Column address
High
High
pin sampling.
By pin
T T T
w c2 c3