Operation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

12.4

Operation

Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
Pulse output pin
DDR
Normal output/inverted output
Figure 12.2 Overview Diagram of PPG
NDER
Q
Output trigger signal
C
Q PODR D Q NDR
Rev. 1.0, 09/01, page 581 of 904
Internal data bus
D