Bus Cycle Control In Write Cycle - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.10

Bus Cycle Control in Write Cycle

By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS
latency control cycle is disabled.
ø
SDRAMø
Address bus
Precharge-sel
CKE
DQMU, DQML
Data bus
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle is Disabled
Rev. 1.0, 09/01, page 192 of 904
T T
p r
Column address Row address
Row address
PALL ACTV
(SDWCD = 1)
T
c1
Column address
High
NOP
T
c2
WRIT