Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 33

Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ................587
Figure 12.10 Inverted Pulse Output (Example) ..........................................................................588
Figure 12.11 Pulse Output Triggered by Input Capture (Example) ............................................589
Section 13 8-Bit Timers (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer Module ...................................................................592
Figure 13.2 Example of Pulse Output .........................................................................................600
Figure 13.3 Count Timing for Internal Clock Input....................................................................600
Figure 13.4 Count Timing for External Clock Input...................................................................601
Figure 13.5 Timing of CMF Setting ...........................................................................................601
Figure 13.6 Timing of Timer Output ..........................................................................................602
Figure 13.7 Timing of Compare Match Clear.............................................................................602
Figure 13.8 Timing of Clearance by External Reset ...................................................................603
Figure 13.9 Timing of OVF Setting............................................................................................603
Figure 13.10 Contention between TCNT Write and Clear .........................................................606
Figure 13.11 Contention between TCNT Write and Increment ..................................................607
Figure 13.12 Contention between TCOR Write and Compare Match ........................................608
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of WDT ..........................................................................................614
Figure 14.2 Operation in Watchdog Timer Mode.......................................................................619
Figure 14.3 Operation in Interval Timer Mode...........................................................................620
Figure 14.4 Writing to TCNT, TCSR, and RSTCSR.................................................................621
Figure 14.5 Contention between TCNT Write and Increment ....................................................622
Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) ......................................623
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1 Block Diagram of SCI .............................................................................................627
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)...................................................658
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode.........................................660
Figure 15.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)..............................................................................................661
Figure 15.5 Sample SCI Initialization Flowchart........................................................................662
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).....................................................663
Figure 15.7 Sample Serial Transmission Flowchart ...................................................................664
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)....................................................665
Figure 15.9 Sample Serial Reception Data Flowchart (1)...........................................................667
Figure 15.9 Sample Serial Reception Data Flowchart (2)...........................................................668
Figure 15.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...........................................670
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart ........................................672
Figure 15.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................673
Rev. 1.0, 09/01, page xxxiii of xliv