Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 333

Address T
A
Address B
A
Legend
Address T = L
A A
Address T = L
B B
Address B = L + SAIDE · (–1)
A A
Address B = L + DAIDE · (–1)
B B
Where : L = Value set in MARA
A
L = Value set in MARB
B
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
SAID DTSZ
· (2 · (N – 1))
DAID DTSZ
· (2 · (M·N – 1))
1st block
Transfer
2nd block
Nth block
Rev. 1.0, 09/01, page 289 of 904
Address T
B
Address B
B