Contention Between Compare Matches A And B - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
Address
Internal write signal
TCNT
TCOR
Compare match signal
Figure 13.12 Contention between TCOR Write and Compare Match
13.8.4

Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.4.
Table 13.4 Timer Output Priorities
Output Setting
Toggle output
1 output
0 output
No change
Rev. 1.0, 09/01, page 608 of 904
TCOR write cycle by CPU
T
1
TCOR address
N
N
Priority
High
Low
T
2
N+1
M
TCOR write data
Inhibited