Synchronous Dram Clock; Basic Timing - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.5

Synchronous DRAM Clock

When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the &68 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,
SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ
and SDRAMφ. When the frequency multiplication factor of the PLL circuit is ×4, the phase of
SDRAMφ and that of φ are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.
Note: SDRAMφ output timing is shown when the frequency multiplication factor of the PLL
circuit is ×1 or ×2.
T cyc
ø
1/4 T cyc (90˚)
SDRAMø
Figure 6.43 Relationship between φ φ φ φ and SDRAMφ φ φ φ (when PLL frequency multiplication
factor is × × × × 1 or × × × × 2)
6.7.6

Basic Timing

The four states of the basic timing consist of one T (precharge cycle) state, one T (row address
p r
output cycle) state, and the T and two T (column address output cycle) states.
c1 c2
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Rev. 1.0, 09/01, page 184 of 904