Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 12

7.5.12 Multi-Channel Operation .....................................................................................307
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC .....................................................................................................308
7.5.14 DMAC and NMI Interrupts..................................................................................309
7.5.15 Forced Termination of DMAC Operation............................................................309
7.5.16 Clearing Full Address Mode ................................................................................310
7.6 Interrupt Sources ...............................................................................................................311
7.7 Usage Notes ......................................................................................................................312
7.7.1 DMAC Register Access during Operation...........................................................312
7.7.2 Module Stop.........................................................................................................314
7.7.3 Write Data Buffer Function .................................................................................314
TEND Output.......................................................................................................314
7.7.4
Activation by Falling Edge on DREQ Pin ...........................................................315
7.7.5
7.7.6 Activation Source Acceptance .............................................................................316
7.7.7 Internal Interrupt after End of Transfer................................................................316
7.7.8 Channel Re-Setting ..............................................................................................316
Section 8 EXDMA Controller ...........................................................................317
8.1 Features .............................................................................................................................317
8.2 Input/Output Pins ..............................................................................................................319
8.3 Register Descriptions ........................................................................................................319
8.3.1 EXDMA Source Address Register (EDSAR) ......................................................320
8.3.2 EXDMA Destination Address Register (EDDAR) ..............................................320
8.3.3 EXDMA Transfer Count Register (EDTCR).......................................................321
8.3.4 EXDMA Mode Control Register (EDMDR) .......................................................323
8.3.5 EXDMA Address Control Register (EDACR) ....................................................327
8.4 Operation...........................................................................................................................331
8.4.1 Transfer Modes ....................................................................................................331
8.4.2 Address Modes.....................................................................................................332
8.4.3 DMA Transfer Requests ......................................................................................336
8.4.4 Bus Modes ...........................................................................................................336
8.4.5 Transfer Modes ....................................................................................................338
8.4.6 Repeat Area Function...........................................................................................340
8.4.7 Registers during DMA Transfer Operation..........................................................342
8.4.8 Channel Priority Order.........................................................................................346
8.4.9 EXDMAC Bus Cycles (Dual Address Mode)......................................................349
8.4.10 EXDMAC Bus Cycles (Single Address Mode) ...................................................354
8.4.11 Examples of Operation Timing in Each Mode.....................................................359
8.4.12 Ending DMA Transfer .........................................................................................372
8.4.13 Relationship between EXDMAC and Other Bus Masters ...................................373
8.5 Interrupt Sources ...............................................................................................................373
8.6 Usage Notes ......................................................................................................................376
8.6.1 EXDMAC Register Access during Operation .....................................................376
Rev. 1.0, 09/01, page xii of xliv