Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 39

Section 1 Overview
Table 1.1 Pin Arrangement in Each Operating Mode ...................................................................4
Table 1.2 Pin Functions...............................................................................................................10
Section 2 CPU
Table 2.1 Instruction Classifcation..............................................................................................33
Table 2.2 Operation Notation......................................................................................................34
Table 2.3 Data Transfer Instructions...........................................................................................35
Table 2.4 Arithmetic Operations Instructions (1) .......................................................................36
Table 2.4 Arithmetic Operations Instructions (2) .......................................................................37
Table 2.5 Logic Operations Instructions .....................................................................................38
Table 2.6 Shift Instructions .........................................................................................................38
Table 2.7 Bit Manipulation Instructions (1)................................................................................39
Table 2.7 Bit Manipulation Instructions (2)................................................................................40
Table 2.8 Branch Instructions .....................................................................................................41
Table 2.9 System Control Instructions ........................................................................................42
Table 2.10 Block Data Transfer Instructions ............................................................................43
Table 2.11 Addressing Modes...................................................................................................44
Table 2.12 Absolute Address Access Ranges ...........................................................................46
Table 2.13 Effective Address Calculation (1) ...........................................................................48
Table 2.13 Effective Address Calculation (2) ...........................................................................49
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection.................................................................................53
Table 3.2 Pin Functions in Each Operating Mode ......................................................................58
Section 4 Exception Handling
Table 4.1 Exception Types and Priority......................................................................................63
Table 4.2 Exception Handling Vector Table...............................................................................64
Table 4.3 Status of CCR and EXR after Trace Exception Handling...........................................68
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling ..........................69
Section 5 Interrupt Controller
Table 5.1 Pin Configuration........................................................................................................75
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.....................................91
Table 5.3 Interrupt Control Modes..............................................................................................95
Table 5.4 Interrupt Response Times .........................................................................................100
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses .......................101
Section 6 Bus Controller (BSC)
Table 6.1 Pin Configuration......................................................................................................107
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)...........................................138
Table 6.3 Data Buses Used and Valid Strobes..........................................................................143
Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space................156
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.......157
Tables of Contents
Rev. 1.0, 09/01, page xxxix of xliv