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In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.42 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
ø
Address bus
(
)
,
(
)
Read
(
)
Data bus
(
)
Write
(
)
Data bus
or
Note: n = 2 to 5
Figure 6.42 Example of '$&.
T
T
p
r
Row address
High
High
'$&./('$&.
('$&. Output Timing when DDS = 0 or EDDS = 0
'$&.
'$&.
('$&.
('$&.
(RAST = 0, CAST = 1)
T
T
c1
c2
Column address
Rev. 1.0, 09/01, page 179 of 904
T
c3
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