Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 222

When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the DRAM interface, the '$&. or ('$&. output goes low
from the T state.
c1
Figure 6.41 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
ø
Address bus
(
(
Read
Data bus
(
Write
(
Data bus
or
Note: n = 2 to 5
Figure 6.41 Example of '$&.
When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single
address transfer mode, full access (normal access) is always performed. With the DRAM interface,
the '$&. or ('$&. output goes low from the T
Rev. 1.0, 09/01, page 178 of 904
T
p
Row address
( )
,
)
)
)
)
'$&./('$&. ('$&. Output Timing when DDS = 1 or EDDS = 1
'$&. '$&. ('$&. ('$&.
(RAST = 0, CAST = 0)
T T
r c1
Column address
High
High
state.
r
T
c2