Inverted Pulse Output - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer

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to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt

handling routine writes the next output data (H'65) in NDRH.

4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by

writing H'59, H'56, H'95... at successive TGIA interrupts.

If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained

without imposing a load on the CPU.

Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the

inverse of the PODR contents can be output.

Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the

settings of figure 12.9.

Rev. 1.0, 09/01, page 588 of 904

Figure 12.10 Inverted Pulse Output (Example)

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