Addressing Modes And Effective Address Calculation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
2.7

Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode
1 Register direct
2 Register indirect
3 Register indirect with displacement
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address
6 Immediate
7 Program-counter relative
8 Memory indirect
Rev. 1.0, 09/01, page 44 of 904
op
op
op
EA (disp)
op cc
Figure 2.11 Instruction Formats (Examples)
NOP, RTS
r m
r n
ADD.B Rn, Rm
r n r m
MOV.B @(d:16, Rn), Rm
EA (disp) BRA d:16
Symbol
Rn
@ERn
@(d:16,ERn)/@(d:32,ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24/@aa:32
#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@@aa:8