Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 419

Transfer end interrupt
exception handling routine
Transfer continuation
Change register settings
Write 1 to EDA bit
End of interrupt handling
(RTE instruction execution)
End of transfer restart
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA
bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared.
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is
cleared.
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
processing
routine
processing
End Interrupt Occurred
Transfer restart after end
of interrupt handling routine
Clear IRF bit to 0
[1]
End of interrupt handling
[2]
Change register settings
[3]
Write 1 to EDA bit
End of transfer restart
processing
[4]
[5]
routine
[6]
[7]
Rev. 1.0, 09/01, page 375 of 904