Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 249

by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the
synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.59 shows
the setting timing of the mode in the synchronous DRAM.
T T T T
p r c1 c2
ø
SDRAMø
Address bus
Mode setting value
Mode setting value
Precharge-sel
CKE
High
PALL NOP MRS NOP
Figure 6.59 Synchronous DRAM Mode Setting Timing
Rev. 1.0, 09/01, page 205 of 904