Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 400

ø
Address bus
Bus release
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when (7(1' output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
ø
Address bus
Bus release
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
('5(4 Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address ('5(4
('5(4 ('5(4
mode transfer activated by the ('5(4 pin falling edge.
Rev. 1.0, 09/01, page 356 of 904
DMA write DMA write
Bus release
DMA write
Bus release
DMA write
Bus release Bus release
DMA write
Bus release
DMA write
Last Bus release
transfer
cycle
DMA write
Last transfer cycle Bus
release