Wait Control Registers Ah, Al, Bh, And Bl (Wtcrah, Wtcral, Wtcrbh, And Wtcrbl) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
In addition, CAS latency is set when a synchronous DRAM is connected.
• WTCRAH
Bit Bit Name
−
15
14 W72
13 W71
12 W70
−
11
Initial Value R/W
0 R
1 R/W
1 R/W
1 R/W
0 R
Description
Reserved
This bit is always read as 0 and cannot be
modified.
Area 7 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 1.0, 09/01, page 111 of 904