Dma Write Enable Register (Dmawer) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

7.3.6

DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit Bit Name

7
to
4
3 WE1B
2 WE1A
1 WE0B
0 WE0A
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Rev. 1.0, 09/01, page 266 of 904
Initial Value R/W
−
0
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Write Enable 1B
Enables or disables writes to all bits in
DMACR1B, bits 11, 7, and 3 in DMABCR, and
bit 5 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 1A
Enables or disables writes to all bits in
DMACR1A, and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0B
Enables or disables writes to all bits in
DMACR0B, bits 9, 5, and 1 in DMABCR, and bit
4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0A
Enables or disables writes to all bits in
DMACR0A, and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled