Interrupt Sources - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Clearing full
address mode
Stop the channel
Initialize DMACR
Clear FAE bit to 0
Initialization;
operation halted
Figure 7.37 Example of Procedure for Clearing Full Address Mode
7.6

Interrupt Sources

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Source
Interrupt
Name Short Address Mode
DMTEND0A Interrupt due to end of
transfer on channel 0A
DMTEND0B Interrupt due to end of
transfer on channel 0B
DMTEND1A Interrupt due to end of
transfer on channel 1A
DMTEND1B Interrupt due to end of
transfer on channel 1B
[1] Clear both the DTE bit and DTME bit in
DMABCRL to 0, or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0. Also clear the corresponding
DTIE bit to 0 at the same time.
[1]
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
[2]
[3]
Full Address Mode
Interrupt due to end of
transfer on channel 0
Interrupt due to break in
transfer on channel 0
Interrupt due to end of
transfer on channel 1
Interrupt due to break in
transfer on channel 1
Interrupt
Priority Order
High
Low
Rev. 1.0, 09/01, page 311 of 904