Synchronous Dram Interface; Setting Continuous Synchronous Dram Space - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7

Synchronous DRAM Interface

In the H8S/2378R Series, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: * The synchronous DRAM interface is not supported in the H8S/2378 series.
6.7.1

Setting Continuous Synchronous DRAM Space

Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
RMTS2 RMTS1
0 0
1
1 0
1
With continuous synchronous DRAM space, &65, &66, &67 pins are used as 5$6, &$6, :(
signal. The (2() pin of the synchronous DRAM is used as the CKE signal, and the &68 pin is
used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous
synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for
the continuous synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining 5$6, &$6, :(, and
address-precharge-setting command (Prechrge-sel) output on the upper column addresses.
Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
Rev. 1.0, 09/01, page 180 of 904
RMTS0 Area 5
1 Normal space Normal space Normal space DRAM space
0 Normal space Normal space DRAM space
1 DRAM space
0 Continuous synchronous DRAM space*
1 Mode settings of synchronous DRAM
0 Reserved (setting prohibited)
1 Continuous DRAM space
Area 4 Area 3
DRAM space DRAM space
Area 2
DRAM space
DRAM space