Basic Timing - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.6.5

Basic Timing

Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and the T
ø
Address bus
(
,
(
(
Read
Data bus
(
Write
(
Data bus
Note: n = 2 to 5
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the 5' signal is output as the 2( signal for DRAM. When
connecting DRAM provided with an EDO page mode, the 2( signal should be connected to the
(2( ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the 2( signal for DRAM
space to be output from a dedicated 2( pin. In this case, the 2( signal for DRAM space is output
and two T
c1 c2
T
p
Row address
)
)
)
)
)
(precharge cycle) state, one T
p
(column address output cycle) states.
T
r
High
High
(row address
r
T T
c1 c2
Column address
Rev. 1.0, 09/01, page 159 of 904