Instructions That Disable Interrupts; Times When Interrupts Are Disabled; Interrupts During Execution Of Eepmov Instruction; Change Of Irq Pin Select Register (Itsr) Setting - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

5.7.2

Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3

Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W
MOV.W
BNE
5.7.5

Change of IRQ Pin Select Register (ITSR) Setting

When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15) of
ISR may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.
R4,R4
L1
Rev. 1.0, 09/01, page 103 of 904