Section 23 List Of Registers; Register Addresses (Address Order) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.

1. Register addresses (address order)

• Registers are listed from the lower allocation addresses.
• Reserved addresses are indicated by  in the register name column. Do not access to reserved
addresses.
• For the addresses of 16 or 32 bits, the MSB-side address is described.
• Registers are classified by functional modules.
• The access size is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
• For the registers of 16 or 32 bits, the MSB is described first.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
23.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.

Section 23 List of Registers

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