Timing Of On-Chip Peripheral Modules - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

24.3.5

Timing of On-Chip Peripheral Modules

Table 24.10 Timing of On-Chip Peripheral Modules
Conditions: V = 3.0 V to 3.6 V, AV
CC
ø = 8 MHz to 33 MHz, T
T = –40°C to +85°C (wide-range specifications)
a
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
PPG Pulse output delay time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time t
Timer clock
pulse width
8-bit timer Timer output delay time
Timer reset input setup time t
Timer clock input setup time t
Timer clock
pulse width
WDT Overflow output delay time
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
= 3.0 V to 3.6 V, V
CC
= –20°C to +75°C (regular specifications),
a
Symbol Min
t
PWD
t
PRS
t
PRH
t
POD
t
TOCD
t
TICS
TCKS
Single-edge t
TCKWH
specification
Both-edge t
TCKWL
specification
t
TMOD
TMRS
TMCS
Single-edge t
TMCWH
specification
Both-edge t
TMCWL
specification
t
WOVD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
= 3.0 V to AV
ref
Max
— 40
25 —
25 —
— 40
— 40
25 —
25 —
1.5 —
2.5 —
— 40
25 —
25 —
1.5 —
2.5 —
— 40
4 —
6 —
0.4 0.6
— 1.5
— 1.5
— 40
40 —
40 —
30 —
Rev. 1.0, 09/01, page 885 of 904
, V = AV = 0 V,
CC SS SS
Unit Test Conditions
ns Figure 24.33
ns
ns
ns Figure 24.34
ns Figure 24.35
ns
ns Figure 24.36
t
cyc
t
cyc
ns Figure 24.37
ns Figure 24.39
ns Figure 24.38
t
cyc
t
cyc
ns Figure 24.40
t Figure 24.41
cyc
t
Scyc
t
cyc
ns Figure 24.42
ns
ns
ns Figure 24.43