Column Address Output Cycle Control - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

from both the 5' pin and the (2() pin, but in external read cycles for other than DRAM space,
the signal is output only from the 5' pin.
6.6.6

Column Address Output Cycle Control

The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (&$6 pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.22
shows an example of the timing when a 3-state column address output cycle is selected.
ø
Address bus
(
,
(
( )
Read
Data bus
(
Write
( )
Data bus
Note: n = 2 to 5
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle
Rev. 1.0, 09/01, page 160 of 904
T
p
Row address
)
)
)
T T
r c1
High
High
(RAST = 0)
T T
c2 c3
Column address