Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 318

Address T
Address B
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data
transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or
DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.4 shows an example of the setting procedure for sequential mode.
Rev. 1.0, 09/01, page 274 of 904
Figure 7.3 Operation in Sequential Mode
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Legend
Address T = L
DTID
Address B = L + (–1)
Where : L = Value set in MAR
N = Value set in ETCR
IOAR
DTSZ
· (2 · (N – 1))