Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 11

6.10 Write Data Buffer Function...............................................................................................230
6.11 Bus Release .......................................................................................................................231
6.11.1 Operation..............................................................................................................231
6.11.2 Pin States in External Bus Released State............................................................233
6.11.3 Transition Timing ................................................................................................234
6.12 Bus Arbitration..................................................................................................................236
6.12.1 Operation..............................................................................................................236
6.12.2 Bus Transfer Timing ............................................................................................236
6.13 Bus Controller Operation in Reset ....................................................................................238
6.14 Usage Notes ......................................................................................................................238
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode .............238
6.14.2 External Bus Release Function and Software Standby ........................................238
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing ...............238
6.14.4 BREQO Output Timing .......................................................................................239
6.14.5 Notes on Usage of the Synchronous DRAM........................................................239
Section 7 DMA Controller (DMAC) ................................................................ 241
7.1 Features .............................................................................................................................241
7.2 Input/Output Pins ..............................................................................................................243
7.3 Register Descriptions ........................................................................................................243
7.3.1 Memory Address Registers (MARA and MARB) ...............................................244
7.3.2 I/O Address Registers (IOARA and IOARB) ......................................................245
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)...................................245
7.3.4 DMA Control Registers (DMACRA and DMACRB) .........................................247
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) .............254
7.3.6 DMA Write Enable Register (DMAWER) ..........................................................266
7.3.7 DMA Terminal Control Register (DMATCR).....................................................268
7.4 Activation Sources ............................................................................................................269
7.4.1 Activation by Internal Interrupt Request..............................................................269
7.4.2 Activation by External Request............................................................................270
7.4.3 Activation by Auto-Request.................................................................................270
7.5 Operation...........................................................................................................................271
7.5.1 Transfer Modes ....................................................................................................271
7.5.2 Sequential Mode ..................................................................................................273
7.5.3 Idle Mode .............................................................................................................275
7.5.4 Repeat Mode ........................................................................................................277
7.5.5 Single Address Mode ...........................................................................................280
7.5.6 Normal Mode .......................................................................................................283
7.5.7 Block Transfer Mode ...........................................................................................286
7.5.8 Basic Bus Cycles..................................................................................................292
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles ...............................................292
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles.............................................300
7.5.11 Write Data Buffer Function .................................................................................306
Rev. 1.0, 09/01, page xi of xliv