Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 337

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Address bus
Bus release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when 7(1' output is enabled, 7(1' output goes low in the transfer end cycle.
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which 7(1'
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
DMA DMA
read
write
Bus release
DMA DMA
read
write
Bus release
Rev. 1.0, 09/01, page 293 of 904
DMA DMA DMA
read
write dead
Last transfer
cycle
Bus
release