Bus Controller Operation In Reset; Usage Notes; External Bus Release Function And All-Module-Clocks-Stopped Mode; External Bus Release Function And Software Standby - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer

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External Bus Release: When the %5(4 pin goes low and an external bus release request is

issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.

External bus release can be performed on completion of an external bus cycle.

Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any

executing bus cycle is aborted.

In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with

the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =

H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =

H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered

in which the clock is also stopped for the bus controller and I/O ports. In this state, the external

bus release function is halted. To use the external bus release function in sleep mode, the ACSE

bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-

module-clocks-stopped mode is executed in the external bus released state, the transition to all-

module-clocks-stopped mode is deferred and performed until after the bus is recovered.

In this LSI, internal bus master operation does not stop even while the bus is released, as long as

the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP

instruction to place the chip in software standby mode is executed while the external bus is

released, the transition to software standby mode is deferred and performed after the bus is

Also, since clock oscillation halts in software standby mode, if %5(4 goes low in this mode,

indicating an external bus release request, the request cannot be answered until the chip has

recovered from the software standby state.

CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the

BREQOE bit to 1 in BCR beforehand enables the %5(42 signal to be output when a CBR

refresh/auto refresh request is issued.

Note: In the H8S/2378 Series, the auto refresh control is not supported.

Rev. 1.0, 09/01, page 238 of 904

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