Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 238

ø
SDRAMø
Address bus
Precharge-sel
CKE
DQMU
DQML
Upper data bus
Lower data bus
Rev. 1.0, 09/01, page 194 of 904
T T
p r
Column address Row address
Row address
PALL ACTV
Figure 6.50 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)
T T
c1 cl
Column address
High
High
READ NOP
T
c2
High-Z