Input/Output Pin; Register Descriptions - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

(interrupt request
Internal reset signal*
Legend
TCSR
TCNT
RSTCSR
Note: * An internal reset signal can be generated by the register setting.
14.2

Input/Output Pin

Table 14.1 describes the WDT output pin.
Table 14.1 WDT Pin
Name
Watchdog timer overflow
14.3

Register Descriptions

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 14.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
Rev. 1.0, 09/01, page 614 of 904
Interrupt
WOVI
control
signal)
Reset
control
RSTCSR
: Timer control/status register
: Timer counter
: Reset control/status register
Figure 14.1 Block Diagram of WDT
Symbol
:'729)
Overflow
Clock
Clock
select
TCNT TSCR
Module bus
WDT
I/O Function
Output Outputs counter overflow signal in watchdog
timer mode
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
sources
Bus
interface