Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 401

ø
Address bus
DMA control
Channel
[1] Acceptance after transfer enabling;
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start;
[4], [7] When pin high level has been sampled, acceptance is resumed after completion of single cycle.
(As in [1],
Figure 8.26 Example of Single Address Mode Transfer Activated by ('5(4
('5(4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the ('5(4 pin while acceptance via the ('5(4 pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and ('5(4 pin high level sampling for edge sensing is started. If ('5(4
pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes
after the end of the single cycle, and ('5(4 pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
('5(4 ('5(4 Pin Low Level Activation Timing: Figure 8.27 shows an example of single address
('5(4 ('5(4
mode transfer activated by the ('5(4 pin low level.
Bus release DMA single
Transfer source/
Idle Single
Request
clearance period
Request
Minimum 3 cycles
[1] [2] [3]
pin high level sampling is started at rise of ø.
pin low level is sampled at rise of ø, and request is held.)
Bus release
destination
Idle Single
clearance period
Request
Minimum 3 cycles
[4] [5]
Acceptance
resumed
pin low level is sampled at rise of ø, and request is held.
Edge
DMA single Bus release
Transfer source/
destination
Idle
Request
[6] [7]
Acceptance
resumed
('5(4 Pin Falling ('5(4 ('5(4
Rev. 1.0, 09/01, page 357 of 904