Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 32

Figure 11.20 Example of PWM Mode Setting Procedure ..........................................................545
Figure 11.21 Example of PWM Mode Operation (1) .................................................................546
Figure 11.22 Example of PWM Mode Operation (2) .................................................................546
Figure 11.23 Example of PWM Mode Operation (3) .................................................................547
Figure 11.24 Example of Phase Counting Mode Setting Procedure ...........................................548
Figure 11.25 Example of Phase Counting Mode 1 Operation ....................................................549
Figure 11.26 Example of Phase Counting Mode 2 Operation ....................................................550
Figure 11.27 Example of Phase Counting Mode 3 Operation ....................................................551
Figure 11.28 Example of Phase Counting Mode 4 Operation ....................................................552
Figure 11.29 Phase Counting Mode Application Example.........................................................553
Figure 11.30 Count Timing in Internal Clock Operation............................................................557
Figure 11.31 Count Timing in External Clock Operation...........................................................557
Figure 11.32 Output Compare Output Timing............................................................................558
Figure 11.33 Input Capture Input Signal Timing........................................................................558
Figure 11.34 Counter Clear Timing (Compare Match)...............................................................559
Figure 11.35 Counter Clear Timing (Input Capture) ..................................................................559
Figure 11.36 Buffer Operation Timing (Compare Match)..........................................................559
Figure 11.37 Buffer Operation Timing (Input Capture) .............................................................560
Figure 11.38 TGI Interrupt Timing (Compare Match) ...............................................................560
Figure 11.39 TGI Interrupt Timing (Input Capture) ...................................................................561
Figure 11.40 TCIV Interrupt Setting Timing ..............................................................................561
Figure 11.41 TCIU Interrupt Setting Timing ..............................................................................562
Figure 11.42 Timing for Status Flag Clearing by CPU...............................................................562
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation................................563
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................564
Figure 11.45 Contention between TCNT Write and Clear Operations .......................................565
Figure 11.46 Contention between TCNT Write and Increment Operations................................565
Figure 11.47 Contention between TGR Write and Compare Match...........................................566
Figure 11.48 Contention between Buffer Register Write and Compare Match ..........................567
Figure 11.49 Contention between TGR Read and Input Capture ...............................................567
Figure 11.50 Contention between TGR Write and Input Capture...............................................568
Figure 11.51 Contention between Buffer Register Write and Input Capture..............................569
Figure 11.52 Contention between Overflow and Counter Clearing............................................569
Figure 11.53 Contention between TCNT Write and Overflow...................................................570
Section 12 Programmable Pulse Generator (PPG)
Figure 12.1 Block Diagram of PPG ............................................................................................572
Figure 12.2 Overview Diagram of PPG......................................................................................581
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) .................................582
Figure 12.4 Setup Procedure for Normal Pulse Output (Example).............................................583
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) .....................................584
Figure 12.6 Non-Overlapping Pulse Output ...............................................................................585
Figure 12.7 Non-Overlapping Operation and NDR Write Timing .............................................586
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example).............................586
Rev. 1.0, 09/01, page xxxii of xliv