Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 20

15.10.2 Break Detection and Processing...........................................................................701
15.10.3 Mark State and Break Sending.............................................................................701
15.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).....................................................................701
15.10.5 Relation between Writes to TDR and the TDRE Flag .........................................701
15.10.6 Restrictions on Use of DMAC or DTC ................................................................702
15.10.7 Operation in Case of Mode Transition.................................................................702
2
Section 16 I C Bus Interface2 (IIC2) (Option) ....................................................707
16.1 Features .............................................................................................................................707
16.2 Input/Output Pins ..............................................................................................................709
16.3 Register Description..........................................................................................................709
2
16.3.1 I C Bus Control Register A (ICCRA) ..................................................................710
2
16.3.2 I C Bus Control Register B (ICCRB)...................................................................712
2
16.3.3 I C Bus Mode Register (ICMR) ...........................................................................713
2
16.3.4 I C Bus Interrupt Enable Register (ICIER) ..........................................................715
2
16.3.5 I C Bus Status Register (ICSR) ............................................................................717
16.3.6 Slave address register (SAR) ...............................................................................719
2
16.3.7 I C Bus Transmit Data Register (ICDRT)............................................................719
2
16.3.8 I C Bus Receive Data Register (ICDRR) .............................................................719
2
16.3.9 I I C Bus Shift Register (ICDRS).........................................................................719
16.4 Operation...........................................................................................................................720
2
16.4.1 I C Bus Format.....................................................................................................720
16.4.2 Master Transmit Operation ..................................................................................721
16.4.3 Master Receive Operation....................................................................................723
16.4.4 Slave Transmit Operation ....................................................................................725
16.4.5 Slave Receive Operation ......................................................................................727
16.4.6 Noise Canceler .....................................................................................................729
16.4.7 Example of Use....................................................................................................729
16.5 Interrupt Request...............................................................................................................734
16.6 Bit Synchronous Circuit....................................................................................................735
Section 17 A/D Converter .................................................................................737
17.1 Features .............................................................................................................................737
17.2 Input/Output Pins ..............................................................................................................738
17.3 Register Description..........................................................................................................739
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH)..............................................740
17.3.2 A/D Control/Status Register (ADCSR)................................................................741
17.3.3 A/D Control Register (ADCR).............................................................................743
17.4 Operation...........................................................................................................................744
17.4.1 Single Mode .........................................................................................................744
17.4.2 Scan Mode ...........................................................................................................744
17.4.3 Input Sampling and A/D Conversion Time..........................................................745
Rev. 1.0, 09/01, page xx of xliv