Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 268

• Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space
write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to
be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit
in DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
DRAM space read External space read DRAM space read
T T T T T T T T T T
p r c1 c2 i 1 2 3 c1 c2
ø
Address bus
,
,
Data bus
Idle cycle
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space
Access:
Note: In the H8S/2378 Series, the synchronous DRAM interface is not supported.
• Normal space access after a continuous synchronous DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.79 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
Rev. 1.0, 09/01, page 224 of 904