Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 870

Register Name
Timer I/O control register L_0
Timer interrupt enable register_0
Timer status register_0
Timer counter_0
Timer general register A_0
Timer general register B_0
Timer general register C_0
Timer general register D_0
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status rgister_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting,
the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that
for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for
group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
2. For writing, refer to section 14.6.1, Notes on register access.
Rev. 1.0, 09/01, page 826 of 904
Abbrevia-
tion Bit No.
TIORL_0 8
TIER_0 8
TSR_0 8
TCNT_0 16
TGRA_0 16
TGRB_0 16
TGRC_0 16
TGRD_0 16
TCR_1 8
TMDR_1 8
TIOR_1 8
TIER_1 8
TSR_1 8
TCNT_1 16
TGRA_1 16
TGRB_1 16
TCR_2 8
TMDR_2 8
TIOR_2 8
TIER_2 8
TSR_2 8
TCNT_2 16
TGRA_2 16
TGRB_2 16
Address Module
H'FFD3 TPU_0
H'FFD4 TPU_0
H'FFD5 TPU_0
H'FFD6 TPU_0
H'FFD8 TPU_0
H'FFDA TPU_0
H'FFDC TPU_0
H'FFDE TPU_0
H'FFE0 TPU_1
H'FFE1 TPU_1
H'FFE2 TPU_1
H'FFE4 TPU_1
H'FFE5 TPU_1
H'FFE6 TPU_1
H'FFE8 TPU_1
H'FFEA TPU_1
H'FFF0 TPU_2
H'FFF1 TPU_2
H'FFF2 TPU_2
H'FFF4 TPU_2
H'FFF5 TPU_2
H'FFF6 TPU_2
H'FFF8 TPU_2
H'FFFA TPU_2
Data Access
Width States
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2