Pins Used For Dram Interface - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.6.4

Pins Used for DRAM Interface

Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the &65 to &68
pins are in the input state after a reset, set the corresponding DDR to 1 when 5$65 to 5$68
signals are output.
Table 6.6 DRAM Interface Pins
With DRAM
Pin Setting
+:5 :(
&65 5$65/5$6
&66 5$66
&67 5$67
&68 5$68
8&$6 8&$6
/&$6 /&$6
5', 2( 2(
:$,7 :$,7
A15 to A0 A15 to A0
D15 to D0 D15 to D0
Rev. 1.0, 09/01, page 158 of 904
Name
Write enable
Row address strobe 2/
row address strobe
Row address strobe 3
Row address strobe 4
Row address strobe 5
Upper column address
strobe
Lower column address
strobe
Output enable
Wait
Address pins
Data pins
I/O Function
Output Write enable for DRAM space
access
Output Row address strobe when area 2
is designated as DRAM space or
row address strobe when areas
2 to 5 are designated as
continuous DRAM space
Output Row address strobe when area 3
is designated as DRAM space
Output Row address strobe when area 4
is designated as DRAM space
Output Row address strobe when area 5
is designated as DRAM space
Output Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
Output Lower column address strobe
signal for 16-bit DRAM space
access
Output Output enable signal for DRAM
space access
Input Wait request signal
Output Row address/column address
multiplexed output
I/O Data input/output pins