Chip Select Signals - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Only the basic bus interface can be used for area 6.
Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The on-
chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the &6: signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4

Chip Select Signals

This LSI can output chip select signals (&63 to &6:) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of &63 to &6:
signals output timing.
Enabling or disabling of &63 to &6: signals output is set by the data direction register (DDR) bit
for the port corresponding to the &63 to &6: pins.
In expanded mode with on-chip ROM disabled, the &63 pin is placed in the output state after a
reset. Pins &64 to &6: are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals &64 to &6:.
In expanded mode with on-chip ROM enabled, pins &63 to &6: are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals &63 to
&6:.
When areas 2 to 5 are designated as DRAM space, outputs &65 to &68 are used as 5$6#signals.
When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2378R
Series, outputs &65, &66, &67, and &68 are used as 5$6, &$6, :(, and CLK signals.
Rev. 1.0, 09/01, page 140 of 904