Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 41

Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1 TPU Functions ......................................................................................................494
Table 11.2 Pin Configuration ..................................................................................................497
Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)..................................................................501
Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).........................................................501
Table 11.5 TPSC2 to TPSC0 (Channel 0)...............................................................................502
Table 11.6 TPSC2 to TPSC0 (Channel 1)...............................................................................502
Table 11.7 TPSC2 to TPSC0 (Channel 2)...............................................................................503
Table 11.8 TPSC2 to TPSC0 (Channel 3)...............................................................................503
Table 11.9 TPSC2 to TPSC0 (Channel 4)...............................................................................504
Table 11.10 TPSC2 to TPSC0 (Channel 5)...............................................................................504
Table 11.11 MD3 to MD0.........................................................................................................506
Table 11.12 TIORH_0 ..............................................................................................................508
Table 11.13 TIORL_0...............................................................................................................509
Table 11.14 TIOR_1 .................................................................................................................510
Table 11.15 TIOR_2 .................................................................................................................511
Table 11.16 TIORH_3 ..............................................................................................................512
Table 11.17 TIORL_3...............................................................................................................513
Table 11.18 TIOR_4 .................................................................................................................514
Table 11.19 TIOR_5 .................................................................................................................515
Table 11.20 TIORH_0 ..............................................................................................................516
Table 11.21 TIORL_0...............................................................................................................517
Table 11.22 TIOR_1 .................................................................................................................518
Table 11.23 TIOR_2 .................................................................................................................519
Table 11.24 TIORH_3 ..............................................................................................................520
Table 11.25 TIORL_3...............................................................................................................521
Table 11.26 TIOR_4 .................................................................................................................522
Table 11.27 TIOR_5 .................................................................................................................523
Table 11.28 Register Combinations in Buffer Operation..........................................................538
Table 11.29 Cascaded Combinations ........................................................................................541
Table 11.30 PWM Output Registers and Output Pins...............................................................544
Table 11.31 Clock Input Pins in Phase Counting Mode ...........................................................548
Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 ......................................549
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2 ......................................550
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3 .....................................551
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4 ......................................552
Table 11.36 TPU Interrupts.......................................................................................................555
Section 12 Programmable Pulse Generator (PPG)
Table 12.1 PPG I/O Pins .........................................................................................................573
Section 13 8-Bit Timers (TMR)
Table 13.1 Pin Configuration ..................................................................................................593
Table 13.2 Clock Input to TCNT and Count Condition ..........................................................596
Table 13.3 8-Bit Timer Interrupt Sources ...............................................................................605
Rev. 1.0, 09/01, page xli of xliv