Page 1 Hitachi Single-Chip Microcomputer H8/3664 Series H8/3664 HD6433664 H8/3663 HD6433663 H8/3662 HD6433662 H8/3661 HD6433661 H8/3660 HD6433660 H8/3664F-ZTAT™ HD64F3664 Hardware Manual ADE-602-202A Rev. 2.0 9/25/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 10-bit A/D converter, so that they can be used as an embedded microcomputer for a sophisticated control system. This manual describes the hardware of the H8/3664 Series. For details on the H8/3664 Series instruction set, refer to the H8/300H Series Programming Manual.
Page 5 Main Revisions and Additions in this Edition Page Item Description TEST pin is amended to TEST pin Figure 1.1 Block Diagram 2.9.2 Notes on Bit Manipulation Example 1 description added 3.4.2 Interrupt Edge Select Register 2 (IEGR2) Bit 5 description amended Figure 5.9 Pin Connection when not Using Figure amended Subclock...
Page 6 Page Item Description 339, 15.4 Usage Notes Description added • Notes on Start Condition Issuance for Retransmission Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission 16.2.3 A/D Control Register (ADCR) Bit 7 Note added Table 18.2 DC Characteristics (2) Conditions changed Table 18.4 I C Bus Interface Timing...
Page 7: Table Of Contents
Contents Section 1 Overview ......................Features ..........................Internal Block Diagram ...................... Pin Arrangement ........................ Pin Functions........................Section 2 ........................11 Features ..........................11 Address Space and Memory Map ..................12 Register Configuration ....................... 15 2.3.1 General Registers ....................16 2.3.2 Program Counter (PC) ..................
Page 8 Interrupts ..........................51 3.3.1 Interrupt and Vector Address ................51 Interrupt Control Registers ....................53 3.4.1 Interrupt Edge Select Register 1 (IEGR1) ............53 3.4.2 Interrupt Edge Select Register 2 (IEGR2) ............54 3.4.3 Interrupt Enable Register 1 (IENR1) ..............55 3.4.4 Interrupt Flag Register 1 (IRR1) ................
Page 9 Register Descriptions......................82 6.2.1 System Control Register 1 (SYSCR1) ..............82 6.2.2 System Control Register 2 (SYSCR2) ..............83 6.2.3 Module Standby Control Register 1 (MSTCR1) ..........85 Mode Transition Conditions....................87 Sleep Mode......................... 90 6.4.1 Transition to the Sleep Mode ................90 6.4.2 Clearing the Sleep Mode ..................
Page 10 7.4.3 Notes on Use of Boot Mode.................. 112 User Program Mode ......................112 Programming/Erasing Flash Memory ................113 7.6.1 Program/Program-Verify ..................114 7.6.2 Erase/Erase-Verify ....................117 7.6.3 Interrupts during Flash Memory Programming/Erasing ........117 Protection..........................119 7.7.1 Hardware Protection....................119 7.7.2 Software Protection ....................
Page 11 9.3.5 Pin Functions......................148 Port 5 ..........................149 9.4.1 Overview ....................... 149 9.4.2 Register Configuration and Description..............149 9.4.3 Port Data Register 5 (PDR5) ................. 150 9.4.4 Port Control Register 5 (PCR5) ................150 9.4.5 Port Pull-Up Control Register 5 (PUCR5)............151 9.4.6 Port Mode Register 5 (PMR5) ................
Page 12 Section 11 Timer V ......................169 11.1 Overview ..........................169 11.1.1 Features ......................... 169 11.1.2 Block Diagram ...................... 170 11.1.3 Pin Configuration ....................171 11.1.4 Register Configuration ..................171 11.2 Register Descriptions......................172 11.2.1 Timer Counter V (TCNTV) .................. 172 11.2.2 Time Constant Registers A and B (TCORA, TCORB) ........
Page 13 Section 13 Watchdog Timer ....................237 13.1 Overview ..........................237 13.1.1 Features ......................... 237 13.1.2 Block Diagram ...................... 237 13.1.3 Register Configuration ..................238 13.2 Register Descriptions......................238 13.2.1 Timer Control/Status Register WD (TCSRWD) ..........238 13.2.2 Timer Counter WD (TCWD) ................240 13.2.3 Timer Mode Register WD (TMWD) ..............
Page 14 14.8.2 Operation when a Number of Receive Errors Occur Simultaneously ....295 14.8.3 Break Detection and Processing................296 14.8.4 Mark State and Break Detection ................296 14.8.5 Receive Error Flags and Transmit Operation (Synchronous Mode Only).... 296 14.8.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode ..296 14.8.7 Relation between RDR Reads and Bit RDRF ............
Page 15 16.4 Operation ..........................350 16.4.1 Single Mode (SCAN = 0)..................350 16.4.2 Scan Mode (SCAN = 1) ..................352 16.4.3 Input Sampling and A/D Conversion Time ............354 16.4.4 External Trigger Input Timing ................355 16.5 Interrupts ..........................356 16.6 Usage Notes........................356 Section 17 Power Supply Circuit ..................
Page 16 Appendix D Port States in the Different Processing States ........442 Appendix E Model Names ....................443 Appendix F Package Dimensions ..................444...
Page 17: Section 1 Overview
Section 1 Overview Features Table 1.1 Features Item Description H8/300H CPU (upward compatibility with H8/300 CPU at object level) • General-register machine  Sixteen 16-bit registers (also usable as eight 16-bit registers plus sixteen 8-bit registers or eight 32-bit registers) •...
Page 18 Item Description Memory Type No. HD64F3664 (Flash memory version) 32 kbytes 2,048 bytes HD6433664 (Mask ROM version) 32 kbytes 1,024 bytes HD6433663 (Mask ROM version) 24 kbytes 1,024 bytes HD6433662 (Mask ROM version) 16 kbytes 512 bytes HD6433661 (Mask ROM version) 12 kbytes 512 bytes HD6433660...
Page 19 Item Description • C bus Conforms to I C bus interface proposed by Philips Electronics interface • Selectable between single master mode and slave mode • Supports two slave addresses • A/D converter 10-bit resolution • 8-channel analog input pins (selectable between single mode and scan mode) •...
Page 20: Internal Block Diagram
Internal Block Diagram System Subclock clock generator H8/300H generator Data bus (lower) P10/TMOW P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD C bus P22/TXD interface P76/TMOV P75/TMCIV Timer W SCI3 P74/TMRIV Watchdog Timer A timer Timer V P84/FTIOD P57/SCL P83/FTIOC P56/SDA P82/FTIOB P55/WKP5/ADTRG P81/FTIOA A/D converter...
Page 21: Pin Arrangement
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P76/TMOV P14/IRQ0 P75/TMCIV P15/IRQ1 P74/TMRIV P16/IRQ2 P57/SCL P17/IRQ3/TRGV P56/SDA PB4/AN4 PB5/AN5 H8/3664 Series PB6/AN6 Top view P10/TMOW PB7/AN7 P55/WKP5/ADTRG PB3/AN3 P54/WKP4 PB2/AN2 P53/WKP3 PB1/AN1 P52/WKP2...
Page 22 PB3/AN3 P17/IRQ3/TRGV PB2/AN2 P16/IRQ2 P15/IRQ1 PB1/AN1 PB0/AN0 P14/IRQ0 P22/TXD P21/RXD P20/SCK3 H8/3664 Series TEST Top view P84/FTI0D OSC2 P83/FTI0C OSC1 P82/FTI0B P81/FTI0A P50/WKP0 P80/FTCI P51/WKP1 P52/WKP2 P76/TMOV P53/WKP3 P75/TMCIV P54/WKP4 P74/TMRIV P57/SCL P55/WKP5/ADTRG P10/TMOW P56/SDA Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins.
Page 23: Pin Functions
Pin Functions Table 1.2 Pin Functions Pin No. FP-64E Type Symbol FP-64A DP-42S Name and Functions Power Input Power supply: All V pins should source pins be connected to the user system Input Ground: All V pins should be connected to the user system GND (0 V).
Page 24 Pin No. FP-64E Type Symbol FP-64A DP-42S Name and Functions Interrupt Input Non-maskable interrupt request pins input pin IRQ0 to 51 to 54 39 to 42 Input IRQ interrupt request 0 to 3: IRQ3 These are input pins for edge- sensitive external interrupts, with a selection of rising or falling edge.
Page 25 Pin No. FP-64E Type Symbol FP-64A DP-42S Name and Functions Serial com- Output SCI3 transmit data output: This is munication the data output pin. interface Input SCI3 receive data input: This is (SCI) the data input pin. SCK3 Output SCI3 clock I/O: This is the clock I/O pin.
Page 27: Section 2 Cpu
Section 2 CPU Features The H8/3664 Series has an H8/300H CPU with an internal 32-bit architecture that is upward- compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. The H8/300H CPU has the following features.
Page 28: Address Space And Memory Map
Transition to low-power state by SLEEP instruction Address Space and Memory Map The address space of the H8/3664 Series CPU is 64 kbytes, which includes the program area and the data area. Figures 2.1 and 2.2 show the memory map.
Page 29 HD6433660 HD64F3664 HD6433661 (Mask ROM version) (Flash memory version) (Mask ROM version) H'0000 H'0000 H'0000 Interrupt vector Interrupt vector Interrupt vector H'0033 H'0033 H'0033 H'0034 H'0034 H'0034 On-chip ROM (8 kbytes) On-chip ROM (12 kbytes) H'1FFF H'2FFF On-chip ROM (32 kbytes) H'7FFF Not used Not used...
Page 30 HD6433662 HD6433663 HD6433664 (Mask ROM version) (Mask ROM version) (Mask ROM version) H'0000 H'0000 H'0000 Interrupt vector Interrupt vector Interrupt vector H'0033 H'0033 H'0033 H'0034 H'0034 H'0034 On-chip ROM (16 kbytes) On-chip ROM (24 kbytes) H'3FFF On-chip ROM (32 kbytes) H'5FFF H'7FFF Not used...
Page 31: Register Configuration
Register Configuration The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. Control registers are 24-bit program counter (PC) and 8-bit condition code register (CCR). General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0...
Page 32: General Registers
2.3.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 33: Program Counter (Pc)
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Relationship between Stack Pointer and Stack Area 2.3.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
Page 34 Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
Page 35: Data Formats
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 36 General Data Type Register Data Format Word data Word data Longword data Notation ERn: General register General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats (2)
Page 37: Memory Data Formats
2.4.2 Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 38: Instruction Set
Instruction Set 2.5.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions. Tables 2.1 to 2.8 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register)
Page 39 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3664 Series. Rs → (EAs) MOVTPE Cannot be used in the H8/3664 Series.
Page 40 Table 2.2 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 41 Instruction Size* Function 0 – Rd → Rd B/W/L Takes the two’s complement (arithmetic complement) of data in a general register. Rd (sign extension) → Rd EXTS Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit.
Page 42 Table 2.3 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 43 Table 2.5 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 44 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry...
Page 45 Table 2.6 Branching Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 46 Table 2.7 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 47 Table 2.8 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 48: Basic Instruction Formats
2.5.2 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc field). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 49: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In the H8/3664 Series, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.6.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.9. Each instruction uses a subset of these addressing modes.
Page 50 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Page 51: Effective Address Calculation
2.6.2 Effective Address Calculation Table 2.11 explains how an effective address (EA) is calculated in each addressing mode. In the H8/3664 Series, the upper 8 bits of the calculated address are ignored in order to generate a 16-bit effective address.
Page 52 Table 2.11 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Effective Address Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) General register contents Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) General register contents disp Sign extension disp...
Page 53 Addressing Mode and Effective Address Instruction Format Calculation Effective Address Absolute address @aa:8 @aa:8 H'FFFF @aa:16 16 15 Sign exten- sion @aa:24 Immediate Operand is immediate #xx:8, #xx:16, or #xx:32 data Program-counter relative @(d:8, PC) or @(d:16, PC) PC contents Sign exten- disp...
Page 54 Memory indirect @@aa:8 H'0000 16 15 Memory H'00 contents Legend: r, rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address Note: In the H8/3664 Series, the upper 8 bits of the calculation result are ignored.
Page 55: Basic Bus Cycle
Basic Bus Cycle CPU operation is synchronized by a system clock (ø) or a subclock (ø ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
Page 56: Access To On-Chip Peripheral Modules
2.7.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width of each register, refer to appendix B, Internal I/O Registers.
Page 57: Cpu States
CPU States 2.8.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. In the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.13.
Page 58: Application Notes
Notes on Data Access to Empty Areas The address space of the H8/3664 Series CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 59: Notes On Bit Manipulation
Example 1: Timer load register and timer counter (This applies to timers B and C. It does not apply to the H8/3664 Series.) Figure 2.15 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place.
Page 60 Example 2: BSET instruction executed designating port 5 and P5 are designated as input pins, with a low-level signal input at P5 and a high-level signal input at P5 . The remaining pins, P5 to P5 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P5 to high-level output.
Page 61 To avoid this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. [A: Prior to executing BSET] MOV.B #80, The PDR5 value (H'80) is written to a work area in MOV.B...
Page 62 Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 As in the examples above, P5 and P5 are input pins, with a low-level signal input at P5 and a high-level signal input at P5 .
Page 63 To avoid this problem, store a copy of the PCR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR5. [A: Prior to executing BCLR] MOV.B #3F, The PCR5 value (H'3F) is written to a work area in MOV.B...
Page 64: Notes On Use Of The Eepmov Instruction
2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ←...
Page 65: Section 3 Exception Handling
3.1.1 Exception Handling Types Exception handling is performed in the H8/3664 Series when a reset, interrupt, or trap instruction occurs. Table 3.1 shows these three types of exception handling. A trap instruction can always be accepted when the program is being executed.
Page 66: Reset By Watchdog Timer
3.2.2 Reset by Watchdog Timer When the watchdog timer overflows, the chip enters the reset state and reset exception handling begins. The same reset exception handling is carried out as for input at the RES pin. For details on the watchdog timer, see section 13, Watchdog Timer. 3.2.3 Interrupt Immediately after Reset After a reset, if the CPU was to accept an interrupt before the stack pointer (SP) was initialized,...
Page 67: Interrupts
Interrupts 3.3.1 Interrupt and Vector Address The interrupt sources that start the interrupt exception handling include 11 external interrupts and 20 internal interrupts. Table 3.2 shows the interrupts, their priorities, and their vector addresses. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority.
Page 68 Interrupt Source Interrupt Vector Number Vector Address Priority (Reserved by (Reserved by system) H'0028 to H'0029 High system) Timer W Input capture A / compare H'002A to H'002B match A Input capture B / compare match B Input capture C / compare match C Input capture D / compare match D...
Page 69: Interrupt Control Registers
Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address Interrupt edge select register 1 IEGR1 H'70 H'FFF2 Interrupt edge select register 2 IEGR2 H'C0 H'FFF3 Interrupt enable register 1 IENR1 H'10 H'FFF4...
Page 70: Interrupt Edge Select Register 2 (Iegr2)
Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ2. Bit 2—IRQ Bit 2: IEG2 Description Falling edge of IRQ2 pin input is detected (initial value) Rising edge of IRQ2 pin input is detected Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1. Bit 1—IRQ Bit 1: IEG1 Description...
Page 71: Interrupt Enable Register 1 (Ienr1)
Bits 4 to 0—WKP to WKP Edge Select (WPEG4 to WPEG0): Bits 4 to 0 select the input sensing of pins WKP4 to WKP0. Bit n: WPEGn Description Falling edge of WKPn pin input is detected (initial value) Rising edge of WKPn pin input is detected (n = 4 to 0) 3.4.3 Interrupt Enable Register 1 (IENR1)
Page 72: Interrupt Flag Register 1 (Irr1)
Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0—IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ3 to IRQ0 interrupt requests. Bit n: IENn Description Disables interrupt requests from pin IRQn...
Page 73: Wakeup Interrupt Flag Register (Iwpr)
Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved: they are always read as 1 and cannot be modified. Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0—IRQ3 to IRQ0 Interrupt Request Flags (IRRI3 to IRRI0) Bit n: IRRIn Description Clearing conditions:...
Page 74: Interrupt Sources
Interrupt Sources 3.5.1 External Interrupts There are 11 external interrupts: NMI, IRQ3 to IRQ0, and WKP5 to WKP0. • NMI Interrupt NMI interrupt is requested by input signal to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.
Page 75: Interrupt Operations
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.5.3 Interrupt Operations Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller.
Page 76 SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 77 Figure 3.3 Interrupt Sequence...
Page 78: Interrupt Response Time
Notes on Stack Area Use When word data is accessed in the H8/3664 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 79: Notes On Rewriting Port Mode Registers
→ H'FEFC → H'FEFD → H'FEFF BSR instruction MOV. B R1L, @–R7 SP set to H'FEFF Stack accessed beyond SP Contents of PC are lost Notation: Upper byte of program counter Lower byte of program counter R1L: General register R1L Stack pointer Figure 3.4 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when...
Page 80 Table 3.5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions When bit IRQ3 in PMR1 is changed from 0 to 1 while pin IRQ IRR1 IRRI3 is low and bit IEG3 in IEGR1 = 0.
Page 81 Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Page 83: Section 4 Address Break
Section 4 Address Break Overview The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Page 84: Register Configuration
4.1.2 Register Configuration Table 4.1 shows the address break register configuration. Table 4.1 Address Break Registers Name Abbrev. Initial Value Address Address break control register ABRKCR H'80 H'FFC8 Address break status register ABRKSR H'3F H'FFC9 Break address register (H) BARH H'FF H'FFCA Break address register (L)
Page 85 Bits 6 and 5—Condition Select (CSEL1, CSEL0): Bits 6 and 5 set address break conditions. When CSEL1=0 and CSEL0=0, data is not compared regardless of the values of DCMP1 and DCMP0. Bit 6: CSEL1 Bit 5: CSEL0 Description Instruction execution cycle (Initial value) CPU data read cycle CPU data write cycle...
Page 86: Address Break Status Register (Abrksr)
Table 4.2 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits I/O register space...
Page 87: Break Address Registers (Barh, Barl)
Bit 6—Address Break Interrupt Enable (ABIE): Bit 6 enables or disables an address break interrupt. Bit 6: ABIE Description Disables an address break interrupt request (Initial value) Enables an address break interrupt request Bits 5 to 0—Reserved Bits: Bits 5 to 0 are reserved; they are always read as 1 and cannot be modified.
Page 88: Break Data Registers (Bdrh, Bdrl)
4.2.4 Break Data Registers (BDRH, BDRL) BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 BDRL2 BDRL1 BDRL0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write BDR (BDRH, BDRL) is a 16-bit read/write register that sets the data for generating an address break interrupt.
Page 89 Figures 4.2 to 4.4 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting Program • ABRKCR = H'80 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 Underline indicates the address 0260 to be stacked.
Page 90 When the interrupt acceptance is prohibited after the RTE (RTB) instruction Register setting Program Underline indicates the • ABRKCR = H'10 0258 address to be stacked. 025A Interrupt 025C MOV.W @H'025A,R0 Interrupt 039A 0260 039C 0262 039E instruc- instruc- instruc- instruc- instruc- tion...
Page 91: Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 92: System Clock Generator
System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. Connecting a Crystal Oscillator: Figure 5.2 shows a typical method of connecting a crystal oscillator.
Page 93 Connecting a Ceramic Oscillator: Figure 5.4 shows a typical method of connecting a ceramic oscillator. = 30 pF ±10% = 30 pF ±10% Figure 5.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points.
Page 94: Subclock Generator
External clock input Open Figure 5.6 Example of External Clock Input Subclock Generator Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 5.7. Follow the same precautions as noted under 5.2 Notes on Board Design.
Page 95: Prescalers
Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X or V and leave pin X open, as shown in figure 5.9. or V Open Figure 5.9 Pin Connection when not Using Subclock Prescalers This LSI is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W).
Page 96: Usage Notes
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping. Usage Notes 5.5.1 Note on Oscillators...
Page 97: Section 6 Power-Down Modes
Section 6 Power-down Modes Overview This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power dissipation is significantly reduced. The module standby mode reduces power dissipation by selectively halting on-chip module functions. Table 6.1 summarizes the six operating modes.
Page 98: Register Descriptions
Register Descriptions 6.2.1 System Control Register 1 (SYSCR1) SSBY STS2 STS1 STS0 NESEL — — — Initial value Read/Write — — — SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'00. Bit 7—Software Standby (SSBY): This bit designates the transition to the sleep mode, subsleep mode, or standby mode.
Page 99: System Control Register 2 (Syscr2)
Bit 3—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (ø ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (ø ) generated by the system clock pulse generator. When ø to 10 MHz, clear NESEL to 0.
Page 100 Bit 5—Direct Transfer on Flag (DTON): This bit designates whether to make direct transitions between the active and subactive modes when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 101: Module Standby Control Register 1 (Mstcr1)
6.2.3 Module Standby Control Register 1 (MSTCR1) — MSTIIC MSTS3 MSTAD MSTWD MSTTW MSTTV MSTTA Initial value Read/Write — MSTCR1 is an 8-bit read/write register that enables each on-chip peripheral module to enter the standby state. Upon reset, MSTCR1 is initialized to H'00. Bit 7—Reserved Bit: This bit is reserved: it is always read as 0 and cannot be modified.
Page 102 Bit 2—Timer W Module Standby (MSTTW): This bit enables timer W to enter the standby state. Bit 2: MSTTW Description Timer W operates normally. (Initial value) Timer W enters the standby state. Bit 1—Timer V Module Standby (MSTTV): This bit enables timer V to enter the standby state. Bit 1: MSTTV Description Timer V operates normally.
Page 103: Mode Transition Conditions
Mode Transition Conditions Figure 6.1 shows the transitions among these operation modes. Table 6.3 shows the transition mode after the SLEEP instruction is executed and when an interrupt occurs. Table 6.4 indicates the internal states in each mode. Reset state LSON = 0 Program halt state Program execution state...
Page 104 Table 6.3 Transition Mode after the SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Instruction Transition Mode due to DTON SSBY SMSEL LSON Execution Interrupt Sleep mode Active mode Subactive mode Subsleep mode Active mode Subactive mode Standby mode Active mode Active mode —...
Page 105 Table 6.4 Internal State in Each Operating Mode Subactive Subsleep Function Active Mode Sleep Mode Mode Mode Standby Mode System clock oscillator Functions Functions Halted Halted Halted Subclock oscillator Functions Functions Functions Functions Functions Instructions Functions Halted Functions Halted Halted operations Registers Retained...
Page 106: Sleep Mode
Sleep Mode 6.4.1 Transition to the Sleep Mode The system goes from the active mode to the sleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 and the DTON and SMSEL bits in SYSCR2 are all cleared to 0. In the sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2.
Page 107: Clearing The Standby Mode
6.5.2 Clearing the Standby Mode The standby mode is cleared by an interrupt or by input at the RES pin. • Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, the standby mode is cleared, and interrupt exception handling starts.
Page 108: Subsleep Mode
Subsleep Mode 6.6.1 Transition to the Subsleep Mode The system goes from the active or subactive mode to the subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, the DTON bit in SYSCR2 is cleared to 0, and the SMSEL bit in SYSCR2 is set to 1.
Page 109: Subactive Mode
Subactive Mode 6.7.1 Transition to the Subactive Mode The subactive mode is entered from the sleep or subsleep mode if an interrupt is requested while the LSON bit in SYSCR2 is set to 1. The operating frequency of the subactive mode is selected from ø...
Page 110: Active Mode
Active Mode 6.8.1 Transition to the Active Mode The active mode is entered from the standby, sleep, or subsleep mode if an interrupt is requested while the LSON bit in SYSCR2 is cleared to 0. The system directly goes to the active mode when a SLEEP instruction is executed while the DTON bit in SYSCR2 is set to 1 and the LSON bit in SYSCR2 is cleared to 0.
Page 111: Direct Transition
Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in the active or subactive mode.
Page 112: Module Standby Mode
• Direct transition from the subactive mode to the active mode When a SLEEP instruction is executed in the subactive mode while the DTON bit in SYSCR2 is set to 1 and the LSON bit in SYSCR2 is cleared to 0, a direct transition is made from the subactive mode to the active mode.
Page 113: Section 7 Rom
Section 7 ROM Features The HD64F3664 has 32 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode •...
Page 114: Overview
Overview 7.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Bus interface/controller Mode pin mode EBR1 FLER FLPWCR Flash memory (32 kbytes) Notation: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 FLER:...
Page 115: On-Board Programming Mode
7.2.2 On-board Programming Mode For flash memory program/erase mode, boot mode and user program mode, in which on-board program/erase is performed, and programmer mode, in which program/erase is performed using a PROM programmer, are available. When the HD64F3664 is activated from the reset state, the HD64F3664 enters different operating modes, depending on the state of the TEST pin, the NMI pin, and the port input level as shown in figure 7.2.
Page 116 When the boot mode is entered, the boot program built in the LSI is activated. The boot mode is shown in figure 7.3. In this mode, the programming control program prepared in the host is received via SCI3, and is serially transmitted to the programming control program area of the on- chip RAM.
Page 117 The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the H8/3664 (originally incorporated in the chip) programming control program and new is started and the programming control program application program beforehand in the host.
Page 118 The programming/erase control program should be prepared in the host or in the flash memory. Host Host Programming/ erase control program New application New application program program H8/3664 H8/3664 SCI3 SCI3 Boot program Boot program Flash memory Flash memory Assessment Assessment program...
Page 119: Block Configuration
7.2.3 Block Configuration The flash memory is divided into four 1-kbyte blocks and one 28-kbyte block. Erasure is performed in this unit. Address H'0000 H'0000 1 kbyte H'0400 1 kbyte H'0800 1 kbyte H'0C00 1 kbyte H'1000 32 kbytes 28 kbytes H'7FFF Address H'7FFF 7.2.4...
Page 120: Register Configuration
7.2.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 7.2. Table 7.2 Register Configuration Register Name Abbreviation Initial Value Address R/W * Flash memory control register 1 FLMCR1 H'00 H'FF90 Flash memory control register 2 FLMCR2 H'00 H'FF91...
Page 121 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1 to 1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5: ESU Description Erase setup cleared...
Page 122: Flash Memory Control Register 2 (Flmcr2)
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1: E Description Erase mode cleared (Initial value) Transition to erase mode [Setting condition] When SWE = 1 and ESU = 1 Bit 0—Program (P): Selects program mode transition or clearing.
Page 123: Erase Block Register 1 (Ebr1)
Bit 7: FLER Description Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Power-on reset or standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 7.7.3, Error Protection Bits 6 to 0—Reserved: These bits always read 0.
Page 124: Flash Memory Power Control Register (Flpwcr)
7.3.4 Flash Memory Power Control Register (FLPWCR) PDWND — — — — — — — Initial value Read/Write FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode.
Page 125: Boot Mode
Bits 6 to 0—Reserved: Write 0 when writing. Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI3 to be used is set to asynchronous mode. The transmission/receive format is 8-bit data, 1 stop-bit, and no parity.
Page 126 H8/3664 measures low period of H'00 data transmitted by host H8/3664 calculates bit rate and sets value in bit rate register After bit rate adjustment, H8/3664 transmits one H'00 data byte to host to indicate end of adjustment...
Page 127: Automatic Sci Bit Rate Adjustment
7.4.1 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) When the boot program is initiated, the boot program measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period.
Page 128: Notes On Use Of Boot Mode
H'F780 Programming control program area (byte) H'FEEF H'FEF0 Boot program area (byte) H'FF7F Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program.
Page 129: Programming/Erasing Flash Memory
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM. Figure 7.8 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.
Page 130: Program/Program-Verify
Notes: 1. Operation is not guaranteed if bits SWE, ESU, PSU, EV, PV, E, and P of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 7.6.1 Program/Program-Verify To write to flash memory, follow the program/program-verify flowchart shown in figure 7.9. Performing programming operations according to this flowchart will enable flash memory to be programmed without subjecting the device to voltage stress or sacrificing data reliability.
Page 131 Write Pulse Application Subroutine Start of programming Start SWE bit ← 1 Enable WDT PSU bit ← 1 Wait 1 µs Wait 50 µs Store 128 bytes of program data in program data area and reprogram data area P bit ← 1 n ←...
Page 132 Table 7.5 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programmed bit Reprogram bit — Remains in erased state Table 7.6 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming Table 7.7...
Page 133: Erase/Erase-Verify
7.6.2 Erase/Erase-Verify To erase flash memory, follow the erase/erase-verify flowchart shown in figure 7.10. 1. Prewriting (setting all data in the memory to be erased to all 0s) is not necessary before erasing. 2. Erasing is performed on one block at a time. Select the block to be erased in erase block register 1 (EBR1).
Page 134 Start of erase SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 Wait 10 µs Disable WDT EV bit ←...
Page 135: Protection
Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.7.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1).
Page 136: Software Protection
7.7.2 Software Protection Software protection can be implemented by clearing the SWE bit in FLMCR1, and by clearing each bit in erase block register 1 (EBR1). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode.
Page 137: Interrupt Handling When Programming/Erasing Flash Memory
Figure 7.11 shows the flash memory state transition diagram. Reset Program mode RES = 0 (hardware protection) Erase mode RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 RES = 0 Error occurrence FLMCR1, FLMCR2, (software standby) EBR1, initialization Error...
Page 138: Flash Memory And Power-Down States
Flash Memory and Power-Down States There are three flash memory operating states in user mode: (1) Normal operating mode: The flash memory can be read and written to at high speed. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating in the subactive mode.
Page 139: Socket Adapter Pin Correspondence Diagram
In programmer mode, set the mode pins to programmer mode (see table 7.11) and input a 10 MHz input clock. Use a PROM programmer that supports the Hitachi 64-kbyte on-chip flash memory microcomputer device type (FZTAT64V5). Table 7.11 shows the pin settings for programmer mode. For the pin names in programmer mode, see section 1.4, Pin Functions.
Page 140 H8/3664F Socket Adapter HN28F101 (32 Pins) (Conversion Pin No. Pin Name to 32-Pin Pin Name Pin No. FP-64A/FP-64E DP-42S Arrangement) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 TEST 0.1 µF Notation I/O7–I/O0: Data input/output A7–A0: Address input Oscillator circuit 10,11 12,13 OSC1, OSC2...
Page 141: Programmer Mode Operation
7.10.2 Programmer Mode Operation Table 7.12 shows how the different operating modes are set when using programmer mode, and table 7.13 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 142: Memory Read Mode
Table 7.13 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
Page 143 Command write Memory read mode Address stable A15–A0 nxtc I/O7–I/O0 Note: Data is latched on the rising edge of WE. Figure 7.14 Timing Waveforms for Memory Read after Memory Write Table 7.15 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: V = 5.0 V ±0.5 V, V = 0 V, T...
Page 144 Memory read mode Other mode command write Address stable A15–A0 nxtc I/O7–I/O0 Note: Do not enable WE and OE at the same time. Figure 7.15 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 7.16 AC Characteristics in Memory Read Mode (Conditions: V = 5.0 V ±0.5 V, = 0 V, T = 25°C ±5°C)
Page 145: Auto-Program Mode
Address stable Address stable A15–A0 I/O7–I/O0 Figure 7.17 CE and OE Clock System Read Timing Waveforms 7.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed.
Page 146 Table 7.17 AC Characteristics in Auto-Program Mode (Conditions: V = 5.0 V ±0.5 V, = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs Figure 7.18 nxtc CE hold time — CE setup time —...
Page 147: Auto-Erase Mode
7.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 148 A15–A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5–I/O0 H'20 H'20 H'00 Figure 7.19 Auto-Erase Mode Timing Waveforms...
Page 149: Status Read Mode
7.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed.
Page 150: Status Polling
Table 7.20 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address error decision erase count exceeded Initial value 0 Indications Normal Command Program-...
Page 151: Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 153: Section 8 Ram
Section 8 RAM Overview H8/3664 Series has 1 kbyte and 512 bytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 155: Section 9 I/O Ports
Section 9 I/O Ports Overview The H8/3664 Series is provided with two 8-bit I/O ports, one 7-bit I/O port, two 3-bit I/O ports, and one 8-bit input-only port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data.
Page 156: Port 1
Port 1 9.2.1 Overview Port 1 is a 7-bit I/O port. Figure 9.1 shows its pin configuration. P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1 Port 1 P14/IRQ0 P10/TMOW Figure 9.1 Port 1 Pin Configuration 9.2.2 Register Configuration and Description Table 9.1 shows the port 1 register configuration. Table 9.1 Port 1 Registers Name...
Page 157: Port Data Register 1 (Pdr1)
9.2.3 Port Data Register 1 (PDR1) — Initial value Read/Write — Note: * Bit 3 is reserved; it is always read as 1 and cannot be modified. PDR1 is an 8-bit register that stores data for port 1 pins P17 to P14 and P12 to P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states.
Page 158: Port Mode Register 1 (Pmr1)
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 to P14 and P12 to P10 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 159 Bit 5—P15/IRQ1 Pin Function Switch (IRQ1): This bit selects whether pin P15/IRQ1 is used as P15 or as IRQ1. Bit 5: IRQ1 Description Functions as P15 I/O pin (Initial value) Functions as IRQ1 input pin Note: Rising or falling edge sensing can be designated for IRQ1. Bit 4—P14/IRQ0 Pin Function Switch (IRQ0): This bit selects whether pin P14/IRQ0 is used as P14 or as IRQ0.
Page 160: Pin Functions
9.2.7 Pin Functions Table 9.2 shows the port 1 pin functions. Table 9.2 Port 1 Pin Functions Pin Functions and Selection Method P17/IRQ3/TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR17 in PCR1. IRQ3 PCR17 IRQ3/TRGV input pin Pin function P17 input pin P17 output pin P16/IRQ2...
Page 161: Mos Input Pull-Up
9.2.8 MOS Input Pull-Up Port 1 has an on-chip MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin.
Page 162: Port 2
Port 2 9.3.1 Overview Port 2 is a 3-bit I/O port, configured as shown in figure 9.2. P22/TXD P21/RXD Port 2 P20/SCK3 Figure 9.2 Port 2 Pin Configuration 9.3.2 Register Configuration and Description Table 9.3 shows the port 2 register configuration. Table 9.3 Port 2 Registers Name...
Page 163: Port Control Register 2 (Pcr2)
9.3.4 Port Control Register 2 (PCR2) — — — — — PCR22 PCR21 PCR20 Initial value Read/Write — — — — — PCR2 is an 8-bit register for controlling whether each of the port 1 pins P22 to P20 functions as an input pin or output pin.
Page 164: Pin Functions
9.3.5 Pin Functions Table 9.4 shows the port 2 pin functions. Table 9.4 Port 2 Pin Functions Pin Functions and Selection Method P22/TXD The pin function depends on bit TXD in PMR1 and bit PCR22 in PCR2. PCR22 Pin function P22 input pin P22 output pin TXD output pin P21/RXD...
Page 165: Port 5
Port 5 9.4.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 9.3. P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 Port 5 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 9.3 Port 5 Pin Configuration 9.4.2 Register Configuration and Description Table 9.5 shows the port 5 register configuration. Table 9.5 Port 5 Registers Name...
Page 166: Port Data Register 5 (Pdr5)
9.4.3 Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 167: Port Pull-Up Control Register 5 (Pucr5)
9.4.5 Port Pull-Up Control Register 5 (PUCR5) — — PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value Read/Write — — PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 168: Pin Functions
9.4.7 Pin Functions Table 9.6 shows the port 5 pin functions. The output type of SCL and SDA is open-drain, providing direct bus driving capability. Table 9.6 Port 5 Pin Functions Pin Functions and Selection Method P57/SCL The pin function depends on bit PCR57 in PCR5 and bit ICE in I2C. PCR57 Pin function P57 input pin P57 output pin...
Page 169: Mos Input Pull-Up
9.4.8 MOS Input Pull-Up Port 5 has an on-chip MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin.
Page 170: Port 7
Port 7 9.5.1 Overview Port 7 is a 3-bit I/O port, configured as shown in figure 9.4. P76/TMOV Port 7 P75/TMCIV P74/TMRIV Figure 9.4 Port 7 Pin Configuration 9.5.2 Register Configuration and Description Table 9.7 shows the port 7 register configuration. Table 9.7 Port 7 Registers Name...
Page 171: Port Control Register 7 (Pcr7)
9.5.4 Port Control Register 7 (PCR7) — PCR76 PCR75 PCR74 — — — — Initial value Read/Write — — — — — PCR7 is an 8-bit register for controlling whether each of the port 7 pins P76 to P74 functions as an input pin or output pin.
Page 172: Port 8
Port 8 9.6.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 9.5. P84/FTIOD Port 8 P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Figure 9.5 Port 8 Pin Configuration 9.6.2 Register Configuration and Description Table 9.9 shows the port 8 register configuration. Table 9.9 Port 8 Registers Name...
Page 173: Port Data Register 8 (Pdr8)
9.6.3 Port Data Register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 174: Pin Functions
9.6.5 Pin Functions Table 9.10 shows the port 8 pin functions. Table 9.10 Port 8 Pin Functions Pin Functions and Selection Method The pin function depends on bit PCR87 in PCR8. PCR87 Pin function P87 input pin P87 output pin The pin function depends on bit PCR86 in PCR8.
Page 175 Pin Functions and Selection Method P83/FTIOC The pin function depends on bit PCR83 in PCR8 and bit TIOR1 in timer W. Timer W Setting IOC2 IOC1 — IOC0 — — Timer W Setting (1) above (2) above PCR83 — Pin function FTIOC output P83 input pin P83 output pin...
Page 176 Pin Functions and Selection Method P82/FTIOA The pin function depends on bit PCR81 in PCR8 and bit TIOR0 in timer W. Timer W Setting IOA2 IOA1 — IOA0 — — Timer W Setting (1) above (2) above PCR81 — Pin function FTIOA output P81 input pin P81 output pin...
Page 177: Port B
Port B 9.7.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 9.6. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration 9.7.2 Register Configuration and Description Table 9.11 shows the port B register configuration. Table 9.11 Port B Register Name Abbrev.
Page 178: Pin Functions
9.7.4 Pin Functions Table 9.12 shows the port B pin functions. Table 9.12 Port B Pin Functions Pin Functions and Selection Method PBn/ANn Always as below. (n = 7 to 0) Pin function PBn input pin or ANn input pin...
Page 179: Section 10 Timer A
Section 10 Timer A 10.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. 10.1.1 Features Features of timer A are given below.
Page 180: Block Diagram
10.1.2 Block Diagram Figure 10.1 shows a block diagram of timer A. ø ø ø ø ø ø /128 ø TMOW ø ø/8192, ø/4096, ø ø/2048, ø/512, ø ø/256, ø/128, ø ø/32, ø/8 ø IRRTA Notation TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag...
Page 181: Register Configuration
10.1.4 Register Configuration Table 10.2 shows the register configuration of timer A. Table 10.2 Timer A Registers Name Abbrev. Initial Value Address Timer mode register A H'10 H'FFA6 Timer counter A H'00 H'FFA7 10.2 Register Descriptions 10.2.1 Timer Mode Register A (TMA) TMA7 TMA6 TMA5...
Page 182: Timer Counter A (Tca)
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3: Bit 2: Bit 1: Bit 0: Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period...
Page 183: Timer Operation
10.3 Timer Operation 10.3.1 Interval Timer Operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately.
Page 184: Timer A Operation States
10.4 Timer A Operation States Table 10.3 summarizes the timer A operation states. Table 10.3 Timer A Operation States Sub- Sub- Module Operation Mode Reset Active Sleep active sleep Standby Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Clock time base Reset Functions Functions Functions Functions Halted...
Page 185: Section 11 Timer V
Section 11 Timer V 11.1 Overview Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle.
Page 186: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of timer V. TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator ø TCORA Clear TCRV0 TMRIV control Interrupt request control Output TCSRV TMOV control CMIA CMIB Notation: TCORA: Time constant register A TCORB: Time constant register B...
Page 187: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbrev. Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV...
Page 188: Register Descriptions
11.2 Register Descriptions 11.2.1 Timer Counter V (TCNTV) TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 Initial value Read/Write TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input. The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and written by the CPU at any time.
Page 189: Timer Control Register V0 (Tcrv0)
11.2.3 Timer Control Register V0 (TCRV0) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 upon reset and in standby mode, subsleep mode, and subactive mode. Bit 7—Compare Match Interrupt Enable B (CMIEB): Bit 7 enables or disables the interrupt request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV.
Page 190 Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to clear TCNTV, and select compare match A or B or an external reset input. When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also halted.
Page 191: Timer Control/Status Register V (Tcsrv)
11.2.4 Timer Control/Status Register V (TCSRV) CMFB CMFA — Initial value Read/Write R/(W)* R/(W)* R/(W)* — Note: * Bits 7 to 5 can be only written with 0, for flag clearing. TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls compare match output.
Page 192 Bit 5—Timer Overflow Flag (OVF): Bit 5 is a status flag indicating that TCNTV has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 5: OVF Description Clearing conditions: After reading OVF = 1, cleared by writing 0 to OVF (Initial value)
Page 193: Timer Control Register V1 (Tcrv1)
11.2.5 Timer Control Register V1 (TCRV1) — — — TVEG1 TVEG0 TRGE — ICKS0 Initial value Read/Write — — — — TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. TCRV1 is initialized to H'E2 upon reset and in subsleep mode and subactive mode.
Page 194: Timer Operation
11.3 Timer Operation Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0 to H'00, TCSRV to H'10, and TCRV1 to H'E2. Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock, as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1.
Page 195 TCNTV Increment Timing: TCNTV is incremented by an input (internal or external) clock. • Internal clock One of six clocks (ø/128, ø/64, ø/32, ø/16, ø/8, ø/4) divided from the system clock (ø) can be selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 11.2 shows the timing.
Page 196 Overflow flag Set Timing: The overflow flag (OVF) is set to 1 when TCNTV overflows from H'FF to H'00. Figure 11.4 shows the timing. ø TCNTV H'FF H'00 Overflow signal Figure 11.4 OVF Set Timing Compare Match Flag set Timing: Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB.
Page 197 TMOV Output Timing: The TMOV output responds to compare match A or B by remaining unchanged, changing to 0, changing to 1, or toggling, as selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is toggled by compare match A. ø...
Page 198: Timer V Operation Modes
TCNTV Clear Timing by TMRIV: TCNTV can be cleared by a rising edge at the TMRIV pin, as selected by bits CCLR1 and CCLR0 in TCRV0. A TMRIV input pulse width of at least 1.5 system clocks is necessary. Figure 11.8 shows the timing. ø...
Page 199: Application Examples
Table 11.4 Timer V Interrupt Sources Interrupt Description Vector Address CMIA Generated from CMFA H'0022 CMIB Generated from CMFB Generated from OVF 11.3.3 Application Examples Pulse Output with Arbitrary Duty Cycle: Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.
Page 200 Single-Shot Output with Arbitrary Pulse Width and Delay from TRGV Input: The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: •...
Page 201: Application Notes
11.3.4 Application Notes The following types of contention can occur in timer V operation. Contention between TCNTV Write and Counter Clear: If a TCNTV clear signal is generated in the T state of a TCNTV write cycle, clearing takes precedence and the write to the counter is not carried out.
Page 202 Contention between TCNTV Write and Increment: If a TCNTV increment clock signal is generated in the T state of a TCNTV write cycle, the write takes precedence and the counter is not incremented. Figure 11.12 shows the timing. TCNTV write cycle by CPU ø...
Page 203 Contention between TCOR Write and Compare Match: If a compare match is generated in the state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 11.13 shows the timing. TCORA write cycle by CPU ø...
Page 204 Contention between Compare Match A and B: If compare match A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by following the priority order in table 11.5. Table 11.5 Timer Output Priority Order Output Setting Priority Toggle output...
Page 205 Table 11.6 Internal Clock Switching and TCNTV Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCNTV Operation Goes from low level Clock before to low level* switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0 Goes from low Clock before to high*...
Page 206 Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCNTV Operation Goes from high level Clock before to low level* switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0 Goes from high Clock before to high switching Clock after switching...
Page 207: Section 12 Timer W
12.1 Overview The H8/3664 has timer W, a 16-bit timer having output compare and input capture functions. Timer W can count external events and output pulses with a desired duty ratio by compare match between the timer counter and four general registers. Thus, it can be applied to various systems.
Page 208 Table 12.1 summarizes the timer W functions. Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clock: FTCI General registers Period GRC (buffer GRD (buffer (output compare/input specified in register for register for...
Page 209: Block Diagrams
12.1.2 Block Diagrams Figure 12.1 is a block diagram of timer W. Internal clock: ø FTIOA ø/2 Clock FTIOB ø/4 selector ø/8 FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus Notation: TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW:...
Page 210: Input/Output Pins
12.1.3 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Timer W Pins Name Abbreviation Input/Output Function External clock input FTCI Input External clock input pin Input capture/output FTIOA Input/output Output pin for GRA output compare or compare A input pin for GRA input capture Input capture/output FTIOB...
Page 211: Register Configuration
12.1.4 Register Configuration Table 12.3 summarizes the timer W registers. Table 12.3 Timer W Registers Name Abbreviation Initial Value Address Timer mode register W TMRW H'48 H'FF80 Timer control register W TCRW H'00 H'FF81 Timer interrupt enable register W TIERW H'70 H'FF82 Timer status register W...
Page 212: Register Description
12.2 Register Description 12.2.1 Timer Mode Register W (TMRW) — BUFEB BUFEA — PWMD PWMC PWMB Initial value Read/Write — — TMRW is an 8-bit read/write register that selects PWM mode and buffer operation. TMRW is initialized to H'48 by a reset. Bit 7—Counter Start (CTS): Starts and stops TCNT.
Page 213: Timer Control Register W (Tcrw)
Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bit 2—PWM Mode D (PWMD): Selects whether the compare match output pin (FTIOD) operates normally or in PWM mode. Bit 2: PWMD Description FTIOD operates normally (output compare output) (Initial value) FTIOD operates in PWM mode* Note: * The period is specified in GRA.
Page 214 Bit 7—Counter Clear (CCLR): Selects how TCNT is cleared. Bit 7: CCLR Description TCNT is not cleared by GRA compare match (Initial value) TCNT is cleared by GRA compare match Bits 6 to 4—Clock Select (CKS2 to CKS0): These bits select the TCNT clock source from four internal clock sources and one external event.
Page 215: Timer Interrupt Enable Register W (Tierw)
Bit 1—Timer Output Level Setting B (TOB): Sets the value output from the FTIOB pin after reset until the first compare match B (TCNT and GRB matching signal) is generated. After a compare match is generated, FTIOB outputs the value specified in timer I/O control register 0 (IOB2 to IOB0).
Page 216 Bits 6 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Input Capture/Compare Match Interrupt Enable D (IMIED): Enables or disables the IMID interrupt requested by the IMFD flag of TSRW when IMFD is set to 1. Bit 3: IMIED Description IMID interrupt requested by IMFD flag is disabled...
Page 217: Timer Status Register W (Tsrw)
12.2.4 Timer Status Register W (TSRW) — — — IMFD IMFC IMFB IMFA Initial value Read/Write R/(W)* — — — R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. TSRW is an 8-bit read/write register that shows the TCNT overflow interrupt request and general register (GRA, GRB, GRC, and GRD) compare match or input capture interrupt requests.
Page 218 Bit 2—Input Capture/Compare Match Flag C (IMFC): This status flag indicates a GRC compare match or input capture event has occurred. This flag is cleared by software and set by hardware; it cannot be set by software. Bit 2: IMFC Description [Clearing condition] (Initial value)
Page 219: Timer I/O Control Register 0 (Tior0)
12.2.5 Timer I/O Control Register 0 (TIOR0) — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — TIOR0 is an 8-bit read/write register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. If the output compare function is selected, TIOR0 also selects the type of output.
Page 220: Timer I/O Control Register 1 (Tior1)
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2: Bit 1: Bit 0: IOA2 IOA1 IOA0 Function GRA is an output No output at compare match (Initial value) compare register 0 output at GRA compare match* 1 output at GRA compare match* Output toggles at GRA compare match*...
Page 221 Bits 6 to 4—I/O Control D2 to D0 (IOD2 to IOD0): These bits select the GRD function. Bit 6: Bit 5: Bit 4: IOD2 IOD1 IOD0 Function GRD is an output No output at compare match (Initial value) compare register 0 output at GRD compare match* 1 output at GRD compare match* Output toggles at GRD compare match*...
Page 222: Timer Counter (Tcnt)
12.2.7 Timer Counter (TCNT) Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT is a 16-bit read/write up-counter that counts the pulses input from the internal or external clock source. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting CCLR of TCRW to 1.
Page 223: Cpu Interface
GRC and GRD can be used as the buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. The general registers are initialized to H'FFFF by a reset. 12.3 CPU Interface 12.3.1 16-Bit Registers TCNT, GRA, GRB, GRC, and GRD are 16-bit registers connected to the CPU by an on-chip 16- bit data bus.
Page 224: Operation
On-chip data bus Module Bus interface data bus TCRW Figure 12.3 8-Bit Register Interface (CPU and TCRW (8 bits)) 12.4 Operation 12.4.1 Overview A summary of operations in the various modes is given below. • Normal Operation Timer W has a timer counter (TCNT) and general registers (GRA to GRD). TCNT is a 16-bit counter that increments the count each time a clock pulse is input, and that can operate as a free-running counter or an external event counter.
Page 225 Counting Operation: TCNT performs free-running or periodic counting operations. Figure 12.4 shows an example of the setup procedure for counting. Counter setup 1. Set bits CKS2 to CKS0 in TCRW to select the counter clock source. 2. For periodic counting, set CCLR Select counter clock in TCRW to 1.
Page 226 TCNT value H'FFFF H'0000 Time CST bit Flag cleared by software Figure 12.5 Free-Running Counter Operation When compare match is selected as the TCNT clear source, TCNT operates as a periodic counter. Select the output compare function for GRA, set bit CCLR in TCRW to 1, and set the count period in GRA.
Page 227 Signal Output by Compare Match: Compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to go to 0, go to 1, or toggle. Figure 12.7 shows an example of the setup procedure for outputting signals by compare match. Output setup 1.
Page 228 Figure 12.9 shows an example of toggle output. TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF Time H'0000 Toggle output FTIOA Toggle output FTIOB Figure 12.9 Toggle Output (1) (TOA = 0, TOB = 1) Figure 12.10 shows another example of toggle output.
Page 229 Input Capture Function: The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. Figure 12.11 shows an example of the procedure for setting up input capture.
Page 230 Figure 12.22 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter. TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA H'1000 H'F000 H'55AA...
Page 231 Buffer Operation: GRC and GRD can be used as buffer registers for GRA and GRB, respectively. The buffer operation differs depending on whether the GR is set as an input capture register or as an output compare register. Table 12.4 shows the register combination for buffer operation. Table 12.4 Register Combination for Buffer Operation General Register Buffer Register...
Page 232 Figure 12.15 shows an example of the procedure for setting up buffer operation. Buffer operation setup 1. Set TIOR to select the input capture or output compare function for a general register. Select GR function 2. Set the BUFEA or BUFEB bit in TMRW to select the buffer operation for a general register.
Page 233 Figure 12.16 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Every time compare match B occurs, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB.
Page 234 Figure 12.17 shows an example of buffer operation when the GRA is set as an input capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edges of the input signal. Every time compare match A occurs, the GRA value is transferred to GRC and the TCNT value is stored in GRA.
Page 235 PWM Operation: In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, or TOD) in TCRW.
Page 236 Figure 12.19 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1). TCNT value Counter cleared by compare match A H'0000...
Page 237 Figures 12.21 and 12.22 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. • TOB, TOC, and TOD = 0: initial output values are set to 0 TCNT value Write to GRB Write to GRB H'0000 Time Duty 0%...
Page 238 • TOB, TOC, and TOD = 1: initial output values are set to 1 TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB When compare match for the period register occurs at the same time as that for the duty TCNT value register, the output signal will not change.
Page 239: Operation Timing
12.4.2 Operation Timing TCNT Count Timing: Figure 12.23 shows the TCNT count timing when the internal clock source is selected. Figure 12.24 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly.
Page 240 Figure 12.25 shows the output compare timing. φ TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 12.25 Output Compare Timing Input Capture Timing: Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1.
Page 241 Timing of Counter Clearing by Compare Match: Figure 12.27 shows the timing when the counter is cleared by compare match A. φ Compare match signal H'0000 TCNT Figure 12.27 Timing of Counter Clearing by Compare Match Buffer Operation Timing: Figures 12.28 and 12.29 show the buffer operation timing. φ...
Page 242 φ Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.29 Buffer Operation Timing (Input Capture) Timing of IMFA to IMFD Flag Setting at Compare Match: If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
Page 243 Timing of IMFA to IMFD Setting at Input Capture: If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.31 shows the timing of the IMFA to IMFD flag setting at input capture.
Page 244: Usage Notes
12.5 Usage Notes Input Pulse Width: The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. Note on Waveform Period Setting: When compare match is selected as the TCNT clearing source, TCNT is cleared in the last state in which the TCNT value matches GRA (when TCNT is updated from the matching count to the next count).
Page 245 Contention between TCNT Write and Increment: If an increment pulse occurs in the T2 state of a TCNT write cycle, writing takes priority and TCNT is not incremented. Figure 12.34 shows this timing. TCNT write cycle φ TCNT address Address Write signal TCNT input clock...
Page 246 Contention between General Register Write and Compare Match in Buffer Operation: If a compare match occurs in the T2 state of a general register write cycle, writing takes priority and the buffer operation (data transfer from the buffer register to the general register) is not performed. Figure 12.35 shows this timing.
Page 247 Contention between Buffer Register Write and Compare Match in Buffer Operation: If a compare match occurs in the T2 state of a buffer register write cycle, the old data (before being updated) in the buffer register is transferred to the general data in a buffer operation. Figure 12.36 shows this timing.
Page 248 Contention between General Register Write and Compare Match: If a compare match (TCNT = GR data before writing) occurs in the T2 state of a general register write cycle, the compare match signal is generated. Figure 12.37 shows this timing. GR write cycle φ...
Page 249 Contention between General Register Write and Input Capture: If a capturing signal is generated in the T2 state of a general register write cycle, writing to GR takes priority and input capture (data transfer from TCNT to GR) is not performed. Figure 12.38 shows this timing. GR write cycle φ...
Page 250 Contention between Buffer Register Write and Input Capture in Buffer Operation: If a capturing signal is generated in the T2 state of a buffer register write cycle, writing to the buffer register takes priority and input capture (data transfer from GR to the buffer register) is not performed.
Page 251 Contention between General Register Read and Input Capture: If a capturing signal is generated in the T1 state of a general register read cycle, the value before input capture is read. Figure 12.40 shows this timing. GR read cycle φ GR address Address Read signal...
Page 252 Internal Clock Switching and TCNT Operation: When the input clock is switched between internal clocks, the TCNT may erroneously increase the count . When an internal clock is selected, the count clock is generated by detecting the rising edges of the internal clock obtained by dividing the system clock (φ).
Page 253: Section 13 Watchdog Timer
Section 13 Watchdog Timer 13.1 Overview The watchdog timer (WDT) is equipped with an 8-bit counter that is incremented by an input clock. An internal chip reset can be executed if the counter overflows because it is not updated normally due to a system crash, etc. 13.1.1 Features Features of the watchdog timer are given below.
Page 254: Register Configuration
13.1.3 Register Configuration Table 13.1 shows the watchdog timer register configuration. Table 13.1 Watchdog Timer Registers Name Abbrev. Initial Value Address Timer control/status register WD TCSRWD H'AA H'FFC0 Timer counter WD TCWD H'00 H'FFC1 Timer mode register WD TMWD H'FF H'FFC2 13.2 Register Descriptions...
Page 255 Bit 5—Bit 4 Write Inhibit (B4WI): Bit 5 controls writing of data to bit 4 of TCSRWD. Bit 5: B4WI Description Writing to bit 4 is enabled Writing to bit 4 is disabled (Initial value) This bit is always read as 1. Data is not stored if written to this bit. Bit 4—Timer Control/Status Register W Write Enable (TCSRWE): Bit 4 controls writing of data to bits 2 and 0 of TCSRWD.
Page 256: Timer Counter Wd (Tcwd)
Bit 1—Bit 0 Write Inhibit (B0WI): Bit 1 controls writing of data to bit 0 of timer control/status register W. Bit 1: B0WI Description Writing to bit 0 is enabled Writing to bit 0 is disabled (Initial value) This bit is always read as 1. Data is not stored if written to this bit. Bit 0—Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed and an internal reset signal has been generated.
Page 257: Timer Mode Register Wd (Tmwd)
13.2.3 Timer Mode Register WD (TMWD) — — — — CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — — — — TMWD is an 8-bit read/write register that selects the input clock. Upon reset, TMWD is initialized to H'FF. Bits 7 to 4—Reserved Bits: Bits 7 to 4 are reserved; they are always read as 1 and cannot be modified.
Page 258: Operation
13.3 Operation The watchdog timer is provided with an 8-bit counter that increments with the input clock. If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD is required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated one base clock (ø) cycle later.
Page 259: Watchdog Timer Operating Modes
13.3.1 Watchdog Timer Operating Modes Watchdog timer operating modes are shown in table 13.2. Table 13.2 Watchdog Timer Operating Modes Operating mode Reset Active Sleep Subactive Subsleep Standby TCWD Reset Functions Functions Halted* Halted* Halted* TCSRWD Reset Functions Functions Functions Retained Retained TMWD...
Page 261: Section 14 Serial Communication Interface 3
Section 14 Serial Communication Interface 3 14.1 Overview Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 14.1.1 Features Features of SCI3 are listed below.
Page 262 • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. • On-chip baud rate generator, allowing any desired bit rate to be selected •...
Page 263: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of SCI3. External Internal clock (ø/64, ø/16, ø/4, ø) Baud rate generator clock Clock Transmit/receive SCR3 control circuit Interrupt request (TEI, TXI, RXI, ERI) Notation: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR:...
Page 264: Pin Configuration
14.1.3 Pin Configuration Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Name Abbrev. Function SCI3 clock SCK3 SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 14.1.4 Register Configuration Table 14.2 shows the SCI3 register configuration.
Page 265: Register Descriptions
14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) Read/Write — — — — — — — — RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically.
Page 266: Transmit Shift Register (Tsr)
14.2.3 Transmit Shift Register (TSR) Read/Write — — — — — — — — TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0).
Page 267: Serial Mode Register (Smr)
14.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value Read/Write SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, subactive, or subsleep mode.
Page 268 Bit 4—Parity Mode (PM): Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled.
Page 269: Serial Control Register 3 (Scr3)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 choose /64, /16, /4, or as the ø ø ø ø clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see section 14.2.8, Bit Rate Register (BRR).
Page 270 Bit 6—Receive Interrupt Enable (RIE): Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
Page 271 Bit 3—Multiprocessor Interrupt Enable (MPIE): Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Page 272: Serial Status Register (Ssr)
Description Bit 1: CKE1 Bit 0: CKE0 Communication Mode Clock Source Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock Clock output Synchronous Reserved Asynchronous External clock Clock input Synchronous External clock Serial clock input Asynchronous Reserved Synchronous...
Page 273 Bit 7—Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7: TDRE Description Transmit data written in TDR has not been transferred to TSR [Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE •...
Page 274 Bit 5—Overrun Error (OER): Bit 5 indicates that an overrun error has occurred during reception. Bit 5: OER Description Reception in progress or completed (Initial value) [Clearing condition] After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception [Setting condition] When reception is completed with RDRF set to 1 Notes: 1.
Page 275 Bit 3—Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. Bit 3: PER Description Reception in progress or completed* (Initial value) [Clearing condition] After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception* [Setting condition] When the number of 1 bits in the receive data plus parity bit does not match...
Page 276: Bit Rate Register (Brr)
Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified. Bit 1: MPBR Description Data in which the multiprocessor bit is 0 has been received (Initial value) Data in which the multiprocessor bit is 1 has been received Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not...
Page 277 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 1200 0.16 –0.70 0.00...
Page 278 ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00 0.16 2400 0.16 0.00 0.00 0.16 4800 0.16 0.00 0.00 0.16 9600...
Page 279 ø (MHz) 14.7456 Bit Rate Error Error Error (bits/s) –0.17 0.70 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16 4800 0.16 0.00 0.16 9600 –0.93 0.00 0.16 19200 –0.93 0.00 0.16 31250 0.00...
Page 280 2. The bit rate error in asynchronous mode is given by the following equation:   ø × 10 × 100   Error (%) = – 1 (N + 1) × B × 64 × 2 2n–1   Table 14.5 shows the maximum bit rate for each frequency.
Page 281 Table 14.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 14.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) — — — — — —...
Page 282 Note: The value set in BRR is given by the following equation: ø × 10 – 1 8 × 2 × B 2n–1 where Bit rate (bit/s) Baud rate generator BRR setting (0 ≤ N ≤ 255) ø: Operating frequency (MHz) Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 14.7.) Table 14.7...
Page 283: Operation
14.3 Operation SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 14.8.
Page 284 Table 14.8 SMR Settings and Corresponding Data Transfer Formats SMR Setting Communication Format Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Multipro- Parity Stop Bit STOP Mode Data Length cessor Bit Length Asynchronous 8-bit data 1 bit mode 2 bits 1 bit 2 bits...
Page 285: Interrupts And Continuous Transmission/Reception
14.3.3 Interrupts and Continuous Transmission/Reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 14.10. Table 14.10 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RDRF When serial reception is performed The RXI interrupt routine reads normally and receive data is the receive data transferred to...
Page 286 ↑ RSR (reception in progress) RSR (reception completed, transfer) RXD pin RXD pin RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 14.2 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓ TSR (transmission in progress) TSR (transmission completed, transfer) TXD pin TXD pin...
Page 287: Operation In Asynchronous Mode
14.4 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 288 Table 14.11 shows the 12 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 14.11 Data Transfer Formats (Asynchronous Mode) SMR Settings Serial Data Transfer Format and Frame Length STOP 8-bit data STOP...
Page 289: Clock
14.4.2 Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 14.9 for details on clock source selection.
Page 290 Figure 14.5 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 291 Transmitting: Figure 14.6 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Page 292 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 293 Receiving: Figure 14.8 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 294 If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 295 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 14.11. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received.
Page 296: Operation In Synchronous Mode
Figure 14.9 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 stop bit ERI request in operation cleared to 0...
Page 297: Data Transfer Format
14.5.1 Data Transfer Format The general data transfer format in synchronous communication is shown in figure 14.10. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't 8 bits care care One transfer data unit (character or frame)
Page 298: Data Transfer Operations
14.5.3 Data Transfer Operations SCI3 Initialization: Data transfer on SCI3 first of all requires that SCI3 be initialized as described in 14.4.3, SCI3 Initialization, and shown in figure 14.5. Transmitting: Figure 14.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Page 299 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 300 Receiving: Figure 14.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing.
Page 301 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 302 Simultaneous Transmit/Receive: Figure 14.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Read bit TDRE Read the serial status register (SSR) and in SSR check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Page 303: Multiprocessor Communication Function
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously with a single instruction. 2.
Page 304 Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver specified by the ID) MPB: Multiprocessor bit...
Page 305 Start Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically.
Page 306 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 307 Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 308 Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 14.19 Example of Multiprocessor Data Reception Flowchart (cont) Figure 14.20 shows an example of the operation when receiving using the multiprocessor format.
Page 309 Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state User RDR data read When data is not...
Page 310: Interrupts
14.7 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 14.13. Table 14.13 SCI3 Interrupt Requests Interrupt Abbreviation...
Page 311: Usage Notes
14.8 Usage Notes The following points should be noted when using SCI3. 14.8.1 Relation between Writes to TDR and Bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
Page 312: Break Detection And Processing
14.8.3 Break Detection and Processing When a framing error is detected, a break can be detected by reading the value of the RXD pin directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 313 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD) Synchronization sampling timing Data sampling timing Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 314: Relation Between Rdr Reads And Bit Rdrf
14.8.7 Relation between RDR Reads and Bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 315: Section 15 I C Bus Interface (Iic)
C Bus Interface (IIC) 15.1 Overview A two-channel I C bus interface is available for the H8/3664 Series. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The...
Page 316: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the I C bus interface. Figure 15.2 shows an example of I/O pin connections to external circuits. The I/O pins are NMOS open drains. Set the upper limit of voltage applied to the power supply (V ) voltage range + 0.3 V, i.e.
Page 317: Pin Configuration
(Master) H8/3664 Series chip (Slave 1) (Slave 2) Figure 15.2 I C Bus Interface Connections (Example: H8/3664 Series Chip as Master) 15.1.3 Pin Configuration Table 15.1 summarizes the input/output pins used by the I C bus interface. Table 15.1 I...
Page 318: Register Configuration
15.1.4 Register Configuration Table 15.2 summarizes the registers of the I C bus interface. Table 15.2 Register Configuration Name Abbreviation Initial Value Address C bus control register ICCR H'01 H'FFC4 C bus status register ICSR H'00 H'FFC5 C bus data register ICDR Undefined H'FFC6*...
Page 319: Register Descriptions
15.2 Register Descriptions 15.2.1 C Bus Data Register (ICDR) ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value — — — — — — — — Read/Write • ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value —...
Page 320 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
Page 321 TDRE Description [Clearing conditions] • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) • When a stop condition is detected in the bus line state after a stop condition is issued with the I C bus format or serial format selected •...
Page 322: Slave Address Register (Sar)
15.2.2 Slave Address Register (SAR) SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 Initial value Read/Write SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 323: Second Slave Address Register (Sarx)
15.2.3 Second Slave Address Register (SARX) SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 Initial value Read/Write SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 324 Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1.
Page 325 Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX bit in the TSCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. TSCR Transfer Rate Bit 0: Bit 5: Bit 4:...
Page 326: I 2 C Bus Control Register (Iccr)
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit.
Page 327 Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I C bus interface module is disabled.
Page 328 Bit 5: MST Bit 4: TRS Operating Mode Slave receive mode (Initial value) Slave transmit mode Master receive mode Master transmit mode Bit 5: MST Description Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2. When bus arbitration is lost after transmission is started in I C bus format master mode Master mode...
Page 329 Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1.
Page 330 When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. Bit 1: IRIC Description [Clearing conditions] (Initial value) 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition;...
Page 331 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
Page 332: I 2 C Bus Status Register (Icsr)
Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1.
Page 333 Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I C bus format slave mode. Bit 6: STOP Description [Clearing conditions] 1. When 0 is written in STOP after reading STOP = 1 2.
Page 334 Bit 4—Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected.
Page 335 Bit 2—Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS.
Page 336: Timer Serial Control Register (Tscr)
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device.
Page 337: Operation
15.3 Operation 15.3.1 C Bus Data Format The I C bus interface has serial and I C bus formats. The I C bus formats are addressing formats and an acknowledge bit is inserted. These are shown in figures 15.3 (a) and (b). The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit.
Page 338: Master Transmit Operation
DATA DATA Figure 15.5 I C Bus Timing Table 15.4 I C Bus Data Format Symbols Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge.
Page 339 sequentially sends the transmission clock and the data written to ICDR using the timing shown in figure 3.1. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. [7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse.
Page 340: Master Receive Operation
Start condition generation (master output) Slave address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address Data 1 (slave output) IRIC IRTR ICDR Data 1 Address + R/W [9] IRIC clearance ICDR writing...
Page 341 [5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to receive next data. [6] Read ICDR.
Page 342: Slave Receive Operation
(master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (slave output) Data 2 Data 3 Data 4 (master output) IRIC IRTR ICDR Data 3 Data 1 Data 2 [6] ICDR read (Data 3)
Page 343 Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Start condition issuance (master output) (slave output) Bit 7...
Page 344: Slave Transmit Operation
(master output) (slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) Data 1 Data 2 (slave output) RDRF Interrupt Interrupt IRIC request request generation generation ICDRS Data 1 Data 2...
Page 345 slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 15.10. [4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse.
Page 346: Iric Setting Timing And Scl Control
15.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred;...
Page 347: Noise Canceler
15.3.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.12 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 348 Start Initialize [1] Initialize Read BBSY in ICCR [2] Test the status of the SCL and SDA lines. BBSY = 0? Set MST = 1 and [3] Select master transmit mode. TRS = 1 in ICCR Write BBSY =1 and [4] Start condition issuance SCP = 0 in ICCR Read IRIC in ICCR...
Page 349 Master receive operation Set TRS = 0 in ICCR Set WAIT = 1 in ICMR [1] Select receive mode. Set ACKB = 0 in ICSR Read ICDR [2] Start receiving. The first read is a dummy read. After reading Clear IRIC in ICCR ICDR, please clear IRIC immediately.
Page 350 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR IRIC = 1? Read AAS and ADZ in ICSR AAS = 1 General call address processing and ADZ = 0? * Description omitted Read TRS in ICCR TRS = 0?
Page 351 Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Write transmit data in ICDR [3] Test for end of transfer. Clear IRIC in ICCR [4] Set slave receive mode.
Page 352: Usage Notes
15.4 Usage Notes • In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
Page 353 • SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle t , as shown in table 17.4 in section 17, Electrical Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz.
Page 354 Table 15.7 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- Influence cation ø = ø = ø = ø = Item Indication (Max.) (Min.) 5 MHz 8 MHz 10 MHz 16 MHz 0.5t (–t...
Page 355 • Note on ICDR Read at end of Master Reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition.
Page 356 [1] Wait for end of 1-byte transfer IRIC = 1? [2] Determine whether SCL is low Clear IRIC in ICSR [3] Issue restart condition instruction for transmission Start condition Other processing issuance? [4] Determine whether start condition is generated or not [5] Set transmit data (slave address + R/W) Read SCL pin SCL = Low?
Page 357: Section 16 A/D Converter
Section 16 A/D Converter 16.1 Overview The H8/3664 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 6.10, Module Standby Mode.
Page 358: Block Diagram
16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – ø/4 Comparator Analog Control circuit multi- plexer Sample-and- ø/8 hold circuit ADTRG interrupt signal Legend: ADCR: A/D control register ADCSR: A/D control/status register ADDRA:...
Page 359: Input Pins
16.1.3 Input Pins Table 16.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AV is the power supply for the analog circuits in the A/D converter. Table 16.1 A/D Converter Pins Abbrevi- Pin Name...
Page 360: Register Configuration
16.1.4 Register Configuration Table 16.2 summarizes the A/D converter’s registers. Table 16.2 A/D Converter Registers Address Name Abbreviation Initial Value H'FFFB0 A/D data register A H ADDRAH H'00 H'FFFB1 A/D data register A L ADDRAL H'00 H'FFFB2 A/D data register B H ADDRBH H'00 H'FFFB3...
Page 361: A/D Control/Status Register (Adcsr)
The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 16.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 16.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD) Analog Input Channel Group 0...
Page 362 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF Description [Clearing condition] (Initial value) Read ADF when ADF =1, then write 0 in ADF. [Setting conditions] • Single mode: A/D conversion ends • Scan mode: A/D conversion ends in all selected channels Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Page 363: A/D Control Register (Adcr)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3: CKS Description Conversion time = 134 states (maximum) (Initial value) Conversion time = 70 states (maximum) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels.
Page 364: Cpu Interface
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger. Bit 7: TRGE Description Starting of A/D conversion by an external trigger is disabled (Initial value) A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) Note: The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the setting of the interrupt edge select register 2 (IEGR2).
Page 365 Upper-byte read Module data bus Bus interface (H'AA) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Lower-byte read Module data bus Bus interface (H'40) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Figure 16.2 A/D Data Register Access Operation (Reading H'AA40)
Page 366: Operation
16.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 367 Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 368: Scan Mode (Scan = 1)
16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
Page 369 Figure 16.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
Page 370: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the input at a time t after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D conversion timing.
Page 371: External Trigger Input Timing
Table 16.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 372: Interrupts
ADIE bit in ADCSR. 16.6 Usage Notes When using the A/D converter, note the following points: 1. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3664 Series is defined as follows: • Resolution Digital output code length of A/D converter •...
Page 373 Digital output Ideal A/D conversion characteristic Quantization error 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 16.7 A/D Converter Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage...
Page 374 2. Allowable Signal-Source Impedance: The analog inputs of the H8/3664 Series are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ. The reason for this rating is that it enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge within the sampling time.
Page 375: Section 17 Power Supply Circuit
17.1 Overview The H8/3664 Series incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 376: When Not Using The Internal Power Supply Step-Down Circuit
17.3 When Not Using the Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and CV pin, as shown in figure 17.2. The external power supply is then input directly to the internal power supply.
Page 377: Section 18 Electrical Characteristics
Section 18 Electrical Characteristics 18.1 Absolute Maximum Ratings Table 18.1 lists the absolute maximum ratings. Table 18.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than Port B –0.3 to V +0.3...
Page 378 Power Supply Voltage and Operating Frequency Range ø (MHz) ø (kHz) 16.0 16.384 10.0 8.192 4.096 • AV = 3.3 V to 5.5 V • AV = 3.3 V to 5.5 V • Active mode • Subactive mode • Sleep mode •...
Page 379: Dc Characteristics
18.2.2 DC Characteristics Table 18.2 lists the DC characteristics. Table 18.2 DC Characteristics (1) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes RES, NMI, Input high...
Page 380 Values Item Symbol Applicable Pins Unit Test Condition Notes Output P10 to P12, – 1.0 — — = 4.0 V to 5.5 V high P14 to P17, –I = 1.5 mA voltage P20 to P22, P50 to P55, – 0.5 — —...
Page 381 Values Item Symbol Applicable Pins Unit Test Condition Notes Pull-up –I P10 to P12, 50.0 — 300.0 µA = 5.0 V, P14 to P17, = 0.0 V current P50 to P55 — 60.0 — = 3.0 V, Reference = 0.0 V value Input All input pins...
Page 382 Values Item Symbol Applicable Pins Unit Test Condition Notes Standby — — µA 32-kHz crystal STBY mode oscillator not used current dissipation RAM data — — retaining voltage Note: * Pin states during current dissipation measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Page 383 Table 18.2 DC Characteristics (2) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Item Symbol Unit Test Condition Allowable output low Output pins — — = 4.0 V to 5.5 V current (per pin) except port 8, SCL and SDA...
Page 384: Ac Characteristics
18.2.3 AC Characteristics Table 18.3 lists the AC characteristics. Tables 18.4 and 18.5 list the PC bus interface timing and the serial interface timing, respectively. Table 18.3 AC Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 385 Values Applicable Reference Item Symbol Pins Unit Test Condition Figure RES pin low — — At power-on and in Figure 18.2 width modes other than those below — — In active mode and sleep mode operation NMI, Input pin high —...
Page 386 Table 18.4 I C Bus Interface Timing = 3.0 V to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise specified. Values Test Reference Item Symbol Unit Condition Figure SCL input cycle time + 600 — —...
Page 387 Table 18.5 Serial Interface (SCI3) Timing = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Input Asynchro- SCK3 — — Figure 18.5 Scyc clock nous...
Page 388: A/D Converter Characteristics
18.2.4 A/D Converter Characteristics Table 18.6 A/D Converter Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Unit Condition Figure Analog power supply voltage Analog input voltage AN0 to...
Page 389: Watchdog Timer
Values Applicable Test Reference Item Symbol Pins Unit Condition Figure Conversion time — — = 4.0 V (single mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error — —...
Page 390: Flash Memory Characteristics (Preliminary)
18.2.6 Flash Memory Characteristics (Preliminary) Table 18.8 Flash Memory Characteristics (Preliminary) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Test Item Symbol Condition Unit Notes Programming time (per 128 bytes) —...
Page 391 Values Test Item Symbol Condition Unit Notes Erase Wait time after SWE — — µs bit setting Wait time after ESU — — µs bit setting Wait time after E bit — 1, 6 setting α Wait time after E bit —...
Page 392: Electrical Characteristics (Mask Rom Version)
18.3 Electrical Characteristics (Mask ROM Version) 18.3.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range ø (MHz) ø (kHz) 16.0 32.768 10.0 • AV = 3.0 V to 5.5 V • AV = 3.0 V to 5.5 V •...
Page 393 Power Supply Voltage and Operating Frequency Range ø (MHz) ø (kHz) 16.0 16.384 10.0 8.192 4.096 • AV = 3.0 V to 5.5 V • AV = 3.0 V to 5.5 V • Active mode • Subactive mode • Sleep mode •...
Page 394: Dc Characteristics
18.3.2 DC Characteristics Table 18.9 lists the DC characteristics. Table 18.9 DC Characteristics (1) = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes RES, NMI, Input high...
Page 395 Values Item Symbol Applicable Pins Unit Test Condition Notes Output P10 to P12, – 1.0 — — = 4.0 V to 5.5 V high P14 to P17, –I = 1.5 mA voltage P20 to P22, P50 to P55, – 0.5 — —...
Page 396 Values Item Symbol Applicable Pins Unit Test Condition Notes Pull-up –I P10 to P12, 50.0 — 300.0 µA = 5.0 V, P14 to P17, = 0.0 V current P50 to P55 — 60.0 — = 3.0 V, Reference = 0.0 V value Input All input pins...
Page 397 Values Item Symbol Applicable Pins Unit Test Condition Notes Standby — — µA 32-kHz crystal STBY mode oscillator not used current dissipation RAM data — — retaining voltage Note: * Pin states during current dissipation measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Page 398 Table 18.9 DC Characteristics (2) = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Item Symbol Unit Test Condition Allowable output low Output pins — — = 4.0 V to 5.5 V current (per pin) except port 8, SCL and SDA...
Page 399: Ac Characteristics
18.3.3 AC Characteristics Table 18.10 lists the AC characteristics. Tables 18.11 and 18.12 list the PC bus interface timing and the serial interface timing, respectively. Table 18.10 AC Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 400 Values Applicable Reference Item Symbol Pins Unit Test Condition Figure RES pin low — — At power-on and in Figure 18.2 width modes other than those below — — In active mode and sleep mode operation NMI, Input pin high —...
Page 401 Table 18.11 I C Bus Interface Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise specified. Values Test Reference Item Symbol Unit Condition Figure SCL input cycle time + 600 — —...
Page 402 Table 18.12 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Input Asynchro- SCK3 — — Figure 18.5 Scyc clock nous...
Page 403: A/D Converter Characteristics
18.3.4 A/D Converter Characteristics Table 18.13 A/D Converter Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Unit Condition Figure Analog power supply voltage Analog input voltage AN0 to...
Page 404: Watchdog Timer
Values Applicable Test Reference Item Symbol Pins Unit Condition Figure Conversion time — — = 4.0 V (single mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error — —...
Page 405: Operation Timing
18.4 Operation Timing OSC1 Figure 18.1 System Clock Input Timing × 0.7 OSC1 Figure 18.2 RES Low Width Timing IRQ0 to IRQ3 WKP0 to WKP5 ADTRG TMCI FTIOA to FTIOD TMCIV, TMRIV TRGV Figure 18.3 Input Timing...
Page 406 STAH STOS SCLH STAS SCLL SDAS SDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 18.4 I C Bus Interface Input/Output Timing SCKW SCK3 Scyc Figure 18.5 SCK3 Input Clock Timing...
Page 407 Scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 18.7. Figure 18.6 Serial Interface 3 Synchronous Mode Input/Output Timing...
Page 408: Output Load Circuit
18.5 Output Load Circuit 2.4 kΩ LSI output pin 12 k Ω 30 pF Figure 18.7 Output Load Condition...
Page 409: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand Program counter...
Page 410 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 411: Data Transfer Instructions
Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs → Rd8 MOV.B @ERs, Rd —...
Page 412 — — — ERn32 → @SP Cannot be used in MOVFPE @aa:16, Rd Cannot be used in the H8/3664 Series the H8/3664 Series MOVTPE Rs, @aa:16 Cannot be used in Cannot be used in the H8/3664 Series the H8/3664 Series...
Page 413: Arithmetic Instructions
2. Arithmetic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 414 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 × Rs8 → Rd16 MULXU.
Page 415 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU.W Rd — —...
Page 416 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 417 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd — — SHAR.L ERd — — SHLL.B Rd —...
Page 418: Bit Manipulation Instructions
5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd — —...
Page 419 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬ (#xx:3 of Rd8) → C BILD #xx:3, Rd —...
Page 420 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) Always — — — — — — — If condition is true then BRA d:16 (BT d:16) — —...
Page 421 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
Page 422 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — CCR → @–SP <vector> → PC CCR ← @SP+ — PC ← @SP+ SLEEP —...
Page 423 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 →...
Page 424: Operation Code Map
Operation Code Map Table A.2 Operation Code Map (1)
Page 425 Table A.2 Operation Code Map (2)
Page 426 Table A.2 Operation Code Map (3)
Page 427: Number Of Execution States
Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates the number of cycles of each type occurring in each instruction.
Page 428 Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access — Internal operation Note: * Depends on which on-chip module is accessed. See section B.1, Register Addresses.
Page 429 Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 430 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd...
Page 431 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8...
Page 432 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @Rs, Rd MOV.B @(d:16, Rs), MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd...
Page 433 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd...
Page 434: Combinations Of Instructions And Addressing Modes
Combinations of Instructions and Addressing Modes Table A.4 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —...
Page 435: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Register Addresses Data Abbre- Module Access Register Name viation Bits Address Name Width State Timer mode register W TMRW H'FF80 Timer W Timer control register W TCRW H'FF81 Timer W Timer interrupt enable register W TIERW H'FF82 Timer W...
Page 436 Data Abbre- Module Access Register Name viation Bits Address Name Width State Transmit data register H'FFAB SCI3 Serial status register H'FFAC SCI3 Receive data register H'FFAD SCI3 A/D data register A ADDRA H'FFB0 A/D converter 8 A/D data register B ADDRB H'FFB2 A/D converter 8...
Page 437 Data Abbre- Module Access Register Name viation Bits Address Name Width State Port data register B PDRB H'FFDD I/O port Port mode register 1 PMR1 H'FFE0 I/O port Port mode register 5 PMR5 H'FFE1 I/O port Port control register 1 PCR1 H'FFE4 I/O port...
Page 438: Register Bits
Register Bits Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TMRW — BUFEB BUFEA — PWMD PWMC PWMB Timer W TCRW CCLR CKS2 CKS1 CKS0 TIERW OVIE — —...
Page 439 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TDRE RDRF TEND MPBR MPBT SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ADDRA A/D converter — — — —...
Page 440 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PDRB I/O port PMR1 IRQ3 IRQ2 IRQ1 IRQ0 — — TMOW PMR5 — — WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PCR1 PCR17 PCR16...
Page 441: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register...
Page 442 Internal data bus PUCR Pull-up MOS PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.2 Port 1 Block Diagram (P16 to P14)
Page 443 Internal data bus PUCR Pull-up MOS PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure C.3 Port 1 Block Diagram (P12, P11)
Page 444 Internal data bus PUCR Pull-up MOS Timer A TMOW PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.4 Port 1 Block Diagram (P10)
Page 445 Internal data bus SCI3 PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.5 Port 2 Block Diagram (P22)
Page 446 Internal data bus SCI3 PDR: Port data register PCR: Port control register Figure C.6 Port 2 Block Diagram (P21)
Page 447 SCI3 SCKIE SCKOE Internal data bus SCKO SCKI PDR: Port data register PCR: Port control register Figure C.7 Port 2 Block Diagram (P20)
Page 448 Internal data bus SDAO/SCLO SDAI/SCLI PDR: Port data register PCR: Port control register Figure C.8 Port 5 Block Diagram (P57, P56)
Page 449 Internal data bus PUCR Pull-up MOS ADTRG PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.9 Port 5 Block Diagram (P55)
Page 450 Internal data bus PUCR Pull-up MOS PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.10 Port 5 Block Diagram (P54 to P50)
Page 451 Internal data bus Timer V TMOV PDR: Port data register PCR: Port control register Figure C.11 Port 7 Block Diagram (P76)
Page 452 Internal data bus Timer V TMCIV PDR: Port data register PCR: Port control register Figure C.12 Port 7 Block Diagram (P75)
Page 453 Internal data bus Timer V TMRIV PDR: Port data register PCR: Port control register Figure C.13 Port 7 Block Diagram (P74)
Page 454 Internal data bus PDR: Port data register PCR: Port control register Figure C.14 Port 8 Block Diagram (P87 to P85)
Page 455 Internal data bus Timer W Output control signals A to D FTIOA FTIOB FTIOC FTIOD PDR: Port data register PCR: Port control register Figure C.15 Port 8 Block Diagram (P84 to P81)
Page 456 Internal data bus Timer W FTCI PDR: Port data register PCR: Port control register Figure C.16 Port 8 Block Diagram (P80)
Page 457 Internal data bus A/D converter CH3 to CH0 Figure C.17 Port B Block Diagram (PB7 to PB0)
Page 458 Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Subactive Active to P1 High Retained Retained High Functions Functions to P1 impedance impedance* to P2 High Retained Retained High Functions Functions impedance impedance*...
Page 459 Appendix E Model Names Package (Package Code) QFP-64 QFP-64 SDIP-42 Product Type (FP-64A) (FP-64E) (DP-42S) H8/3664 Flash memory Standard HD64F3664H HD64F3664FP HD64F3664BP version product Mask ROM Standard HD6433664H HD6433664FP HD6433664BP version product H8/3663 Mask ROM Standard HD6433663H HD6433663FP HD6433663BP version...
Page 460 Appendix F Package Dimensions In case of discrepancy, the package dimensions given in the publication Hitachi Semiconductor Packages apply. 17.2 ± 0.3 Unit: mm *0.37 ± 0.08 0.15 M 0.35 ± 0.06 0° – 8° 0.8 ± 0.3 0.10 Hitachi Code...
Page 461 Unit: mm 12.0 ± 0.2 *0.22 ± 0.05 0.08 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.2 0.10 Hitachi Code FP-64E JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 0.4 g Base material dimension...
Page 462 Unit: mm 37.3 38.6 Max 1.38 Max 15.24 + 0.10 0.25 – 0.05 1.78 ± 0.25 0.48 ± 0.10 0° – 15° Hitachi Code DP-42S JEDEC — EIAJ Conforms Weight (reference value) 4.8 g Figure F.3 DP-42S Package Dimensions...
Page 463 Publication Date: 1st Edition, March 2000 2nd Edition, September 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.

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