Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 823

of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 20.6.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses
H'FFA800 to H'FFBFFF is the area to which the programming control program is transferred
from the host. The boot program area cannot be used until the execution state in boot mode
switches to the programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TxD pin is high. The contents of the CPU
general registers are undefined immediately after branching to the programming control
program. These registers must be initialized at the beginning of the programming control
program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
7. Boot mode can be cleared by reset. Release the reset by setting the MD pin, after waiting at
least 20 states since driving the reset pin low. Boot mode is also cleared when the WDT
overflow reset occurs.
8. Do not change the MD pin input levels in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
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