Port A Data Register (Padr); Port A Register (Porta) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

10.9.2

Port A Data Register (PADR)

PADR stores output data for the port A pins.
Bit Bit Name
7 PA7DR
6 PA6DR
5 PA5DR
4 PA4DR
3 PA3DR
2 PA2DR
1 PA1DR
0 PA0DR
10.9.3

Port A Register (PORTA)

PORTA shows port A pin states.
PORTA cannot be modified.
Bit Bit Name
7 PA7
6 PA6
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
0 PA0
Note: Determined by the states of pins PA7 to PA0.
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
R
—*
R
—*
R
—*
R
—*
R
—*
R
—*
R
—*
R
—*
Description
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Description
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.
Rev. 1.0, 09/01, page 455 of 904