Bit Rate Register (Brr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bit Bit Name
0 SMIF
15.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode Bit Rate
Asynchronous
B =
Mode
Clocked
B =
Synchronous
Mode
Smart Card
B =
Interface Mode
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
ø: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1 CKS0
0 0
0 1
1 0
1 1
Rev. 1.0, 09/01, page 646 of 904
Initial Value R/W
0 R/W
6
ø 10
2n-1
64 2 (N + 1)
6
ø 10
2n-1
8 2 (N + 1)
6
ø 10
2n-1
S 2 (N + 1)
n
0
1
2
3
Description
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart card interface mode
Error
Error (%) = {
B 64
Error (%) = {
B S
SMR Setting
BCP1
0
0
1
1
6
ø 10
-1 }
2n-1
2 (N + 1)
6
ø 10
-1 }
2n-1
2 (N + 1)
BCP0 S
0 32
1 64
0 372
1 256
100
100