Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 396

Bus release
ø
Address bus
DMA control Idle
Channel
Request
Minimum 3 cycles
[1]
[1] Acceptance after transfer enabling;
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start;
[4], [7] When pin high level has been sampled, acceptance is resumed after completion of dead cycle.
(As in [1],
Figure 8.19 Example of Block Transfer Mode Transfer Activated by ('5(4
('5(4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the ('5(4 pin while acceptance via the ('5(4 pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and ('5(4 pin high level sampling for edge sensing is started. If ('5(4
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and ('5(4 pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
('5(4 Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode ('5(4
('5(4 ('5(4
transfer activated by the ('5(4 pin low level.
Rev. 1.0, 09/01, page 352 of 904
One block transfer
DMA read DMA write
Transfer source
Read Write
Request clearance period
[2] [3]
pin high level sampling is started at rise of ø.
pin low level is sampled at rise of ø, and request is held.)
Bus release
Transfer
destination
Idle
Request
Minimum 3 cycles
[4] [5]
Acceptance
resumed
pin low level is sampled at rise of ø, and request is held.
Edge
One block transfer
DMA read DMA write Bus release
Transfer
Transfer source
destination
Read Write Idle
Request clearance period
[6]
Acceptance
resumed
('5(4 Pin Falling ('5(4 ('5(4
[7]